Saved in:
| Main Author: | Prasad, Rohit |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2507.12904 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
NX-CGRA: A Programmable Hardware Accelerator for Core Transformer Algorithms on Edge Devices
by: Prasad, Rohit
Published: (2025)
by: Prasad, Rohit
Published: (2025)
Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA
by: Carpentieri, Nicolò, et al.
Published: (2024)
by: Carpentieri, Nicolò, et al.
Published: (2024)
HALO: Hardware-aware quantization with low critical-path-delay weights for LLM acceleration
by: Juneja, Rohan, et al.
Published: (2025)
by: Juneja, Rohan, et al.
Published: (2025)
Evaluation of CGRA Toolchains
by: Walter, Dominik, et al.
Published: (2025)
by: Walter, Dominik, et al.
Published: (2025)
Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator
by: Hokenmaier, W, et al.
Published: (2024)
by: Hokenmaier, W, et al.
Published: (2024)
J3DAI: A tiny DNN-Based Edge AI Accelerator for 3D-Stacked CMOS Image Sensor
by: Tain, Benoit, et al.
Published: (2025)
by: Tain, Benoit, et al.
Published: (2025)
Spiker+: a framework for the generation of efficient Spiking Neural Networks FPGA accelerators for inference at the edge
by: Carpegna, Alessio, et al.
Published: (2024)
by: Carpegna, Alessio, et al.
Published: (2024)
Towards 3D Acceleration for low-power Mixture-of-Experts and Multi-Head Attention Spiking Transformers
by: Xu, Boxun, et al.
Published: (2024)
by: Xu, Boxun, et al.
Published: (2024)
GAVINA: flexible aggressive undervolting for bit-serial mixed-precision DNN acceleration
by: Fornt, Jordi, et al.
Published: (2025)
by: Fornt, Jordi, et al.
Published: (2025)
HAPM -- Hardware Aware Pruning Method for CNN hardware accelerators in resource constrained devices
by: Peccia, Federico Nicolas, et al.
Published: (2024)
by: Peccia, Federico Nicolas, et al.
Published: (2024)
Building an Open CGRA Ecosystem for Agile Innovation
by: Juneja, Rohan, et al.
Published: (2025)
by: Juneja, Rohan, et al.
Published: (2025)
Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours
by: The Verkor Team, et al.
Published: (2026)
by: The Verkor Team, et al.
Published: (2026)
STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems
by: Vazquez, Daniel, et al.
Published: (2024)
by: Vazquez, Daniel, et al.
Published: (2024)
Monomorphism-based CGRA Mapping via Space and Time Decoupling
by: Tirelli, Cristian, et al.
Published: (2025)
by: Tirelli, Cristian, et al.
Published: (2025)
Exploiting pre-optimized kernels with polyhedral transformations for CGRA compilation
by: Wang, Yuxuan, et al.
Published: (2026)
by: Wang, Yuxuan, et al.
Published: (2026)
Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning
by: Li, Zhaoying, et al.
Published: (2024)
by: Li, Zhaoying, et al.
Published: (2024)
BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge
by: Ji, Yuhao, et al.
Published: (2024)
by: Ji, Yuhao, et al.
Published: (2024)
SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs
by: Bai, Zhenyu, et al.
Published: (2024)
by: Bai, Zhenyu, et al.
Published: (2024)
TReX- Reusing Vision Transformer's Attention for Efficient Xbar-based Computing
by: Moitra, Abhishek, et al.
Published: (2024)
by: Moitra, Abhishek, et al.
Published: (2024)
M$^2$-ViT: Accelerating Hybrid Vision Transformers with Two-Level Mixed Quantization
by: Liang, Yanbiao, et al.
Published: (2024)
by: Liang, Yanbiao, et al.
Published: (2024)
A 28 nm AI microcontroller with tightly coupled zero-standby power weight memory featuring standard logic compatible 4 Mb 4-bits/cell embedded flash technology
by: Kim, Daewung, et al.
Published: (2025)
by: Kim, Daewung, et al.
Published: (2025)
DR-CGRA: Supporting Loop-Carried Dependencies in CGRAs Without Spilling Intermediate Values
by: Hadar, Elad, et al.
Published: (2024)
by: Hadar, Elad, et al.
Published: (2024)
Late Breaking Results: Quamba-SE: Soft-edge Quantizer for Activations in State Space Models
by: Chen, Yizhi, et al.
Published: (2026)
by: Chen, Yizhi, et al.
Published: (2026)
T-REX: A 68-567 μs/token, 0.41-3.95 μJ/token Transformer Accelerator with Reduced External Memory Access and Enhanced Hardware Utilization in 16nm FinFET
by: Moon, Seunghyun, et al.
Published: (2025)
by: Moon, Seunghyun, et al.
Published: (2025)
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
by: Cammarata, Danilo, et al.
Published: (2025)
by: Cammarata, Danilo, et al.
Published: (2025)
Low-power Spike-based Wearable Analytics on RRAM Crossbars
by: Bhattacharjee, Abhiroop, et al.
Published: (2025)
by: Bhattacharjee, Abhiroop, et al.
Published: (2025)
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
by: Al-Qawlaq, Aness, et al.
Published: (2024)
by: Al-Qawlaq, Aness, et al.
Published: (2024)
FeNN-DMA: A RISC-V SoC for SNN acceleration
by: Aizaz, Zainab, et al.
Published: (2025)
by: Aizaz, Zainab, et al.
Published: (2025)
FeNN: A RISC-V vector processor for Spiking Neural Network acceleration
by: Aizaz, Zainab, et al.
Published: (2025)
by: Aizaz, Zainab, et al.
Published: (2025)
GTAC: A Generative Transformer for Approximate Circuits
by: Wang, Jingxin, et al.
Published: (2025)
by: Wang, Jingxin, et al.
Published: (2025)
HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline
by: Guo, Qingyu, et al.
Published: (2024)
by: Guo, Qingyu, et al.
Published: (2024)
FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs
by: Kabir, Ehsan, et al.
Published: (2024)
by: Kabir, Ehsan, et al.
Published: (2024)
MetaDSE: A Few-shot Meta-learning Framework for Cross-workload CPU Design Space Exploration
by: Xue, Runzhen, et al.
Published: (2025)
by: Xue, Runzhen, et al.
Published: (2025)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)
by: Deng, Chenhui, et al.
Published: (2025)
EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
by: Guo, Ping, et al.
Published: (2025)
by: Guo, Ping, et al.
Published: (2025)
DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge Base
by: Ibnat, Zahin, et al.
Published: (2025)
by: Ibnat, Zahin, et al.
Published: (2025)
Automated Multi-Agent Workflows for RTL Design
by: Bhattaram, Amulya, et al.
Published: (2025)
by: Bhattaram, Amulya, et al.
Published: (2025)
Hey AI, Generate Me a Hardware Code! Agentic AI-based Hardware Design & Verification
by: Gadde, Deepak Narayan, et al.
Published: (2025)
by: Gadde, Deepak Narayan, et al.
Published: (2025)
Optimizing Coverage-Driven Verification Using Machine Learning and PyUVM: A Novel Approach
by: Kumari, Suruchi, et al.
Published: (2025)
by: Kumari, Suruchi, et al.
Published: (2025)
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
by: Niu, Juxin, et al.
Published: (2025)
by: Niu, Juxin, et al.
Published: (2025)
Similar Items
-
NX-CGRA: A Programmable Hardware Accelerator for Core Transformer Algorithms on Edge Devices
by: Prasad, Rohit
Published: (2025) -
Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA
by: Carpentieri, Nicolò, et al.
Published: (2024) -
HALO: Hardware-aware quantization with low critical-path-delay weights for LLM acceleration
by: Juneja, Rohan, et al.
Published: (2025) -
Evaluation of CGRA Toolchains
by: Walter, Dominik, et al.
Published: (2025) -
Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator
by: Hokenmaier, W, et al.
Published: (2024)