4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866912490531586048 |
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| author | Kihara, Fuyuki Uenohara, Seiji Awamura, Satoshi Misawa, Naoko Matsui, Chihiro Takeuchi, Ken |
| author_facet | Kihara, Fuyuki Uenohara, Seiji Awamura, Satoshi Misawa, Naoko Matsui, Chihiro Takeuchi, Ken |
| contents | Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. However, there is a problem regarding power consumption and device-derived errors that increase as row parallelism increases. In this paper, a 4T2R ReRAM cell and an 8T SRAM CiM suitable for CiM is proposed. It is shown that adopting the proposed 4T2R ReRAM cell reduces the errors due to variation in ReRAM devices compared to conventional 4T4R ReRAM cells. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2507_13631 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | 4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation Kihara, Fuyuki Uenohara, Seiji Awamura, Satoshi Misawa, Naoko Matsui, Chihiro Takeuchi, Ken Hardware Architecture Computation-in-Memory (CiM) is attracting attention as a technology that can perform MAC calculations required for AI accelerators, at high speed with low power consumption. However, there is a problem regarding power consumption and device-derived errors that increase as row parallelism increases. In this paper, a 4T2R ReRAM cell and an 8T SRAM CiM suitable for CiM is proposed. It is shown that adopting the proposed 4T2R ReRAM cell reduces the errors due to variation in ReRAM devices compared to conventional 4T4R ReRAM cells. |
| title | 4T2R X-ReRAM CiM Array for Variation-tolerant, Low-power, Massively Parallel MAC Operation |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2507.13631 |