Enabling Efficient Hardware Acceleration of Hybrid Vision Transformer (ViT) Networks at the Edge
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arXiv
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| Main Authors: | Dumoulin, Joren, Houshmand, Pouya, Jain, Vikram, Verhelst, Marian |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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