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RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Fuente: arXiv

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Bibliographic Details
Main Authors:	Jin, Pengwei, Huang, Di, Li, Chongxiao, Cheng, Shuyao, Zhao, Yang, Zheng, Xinyao, Zhu, Jiaguo, Xing, Shuyi, Dou, Bohan, Zhang, Rui, Du, Zidong, Guo, Qi, Hu, Xing
Format:	Preprint
Published:	2025
Subjects:	Machine Learning Hardware Architecture
Online Access:	Acceder al recurso
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