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| Main Author: | |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2507.19009 |
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Table of Contents:
- We present a simple ACL2 simulator for the RISC-V 32-bit base instruction set architecture, written in the operational semantics style. Like many other ISA models, our RISC-V state object is a single-threaded object and we prove read-over-write, write-over-write, writing-the-read, and state well-formedness theorems. Unlike some other models, we separate the instruction decoding functions from their semantic counterparts. Accordingly, we verify encoding / decoding functions for each RV32I instruction, the proofs for which are entirely automatic.