Cover Image

SLTarch: Towards Scalable Point-Based Neural Rendering by Taming Workload Imbalance and Memory Irregularity

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Li, Xingyang, Jiang, Jie, Feng, Yu, Gan, Yiming, Zhao, Jieru, Liu, Zihan, Leng, Jingwen, Guo, Minyi
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Cicero: Addressing Algorithmic and Architectural Bottlenecks in Neural Rendering by Radiance Warping and Memory Optimizations
by: Feng, Yu, et al.
Published: (2024)

Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture
by: Feng, Yu, et al.
Published: (2024)

Nebula: Enable City-Scale 3D Gaussian Splatting in Virtual Reality via Collaborative Rendering and Accelerated Stereo Rasterization
by: Zhu, He, et al.
Published: (2025)

StreamGrid: Streaming Point Cloud Analytics via Compulsory Splitting and Deterministic Termination
by: Feng, Yu, et al.
Published: (2025)

Lumina: Real-Time Mobile Neural Rendering by Exploiting Computational Redundancy
by: Feng, Yu, et al.
Published: (2025)

Splatonic: Architecture Support for 3D Gaussian Splatting SLAM via Sparse Processing
by: Huang, Xiaotong, et al.
Published: (2025)

M-ANT: Efficient Low-bit Group Quantization for LLMs via Mathematically Adaptive Numerical Type
by: Hu, Weiming, et al.
Published: (2025)

Nexus Machine: An Active Message Inspired Reconfigurable Architecture for Irregular Workloads
by: Juneja, Rohan, et al.
Published: (2025)

TIMERIPPLE: Accelerating vDiTs by Understanding the Spatio-Temporal Correlations in Latent Space
by: Miao, Wenxuan, et al.
Published: (2025)

CODO: An Automated Compiler for Comprehensive Dataflow Optimization
by: Zhang, Weichuang, et al.
Published: (2026)

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs
by: Gao, Mingzhe, et al.
Published: (2024)

Towards Efficient LUT-based PIM: A Scalable and Low-Power Approach for Modern Workloads
by: Khabbazan, Bahareh, et al.
Published: (2025)

An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
by: Zhang, Weichuang, et al.
Published: (2024)

ICP: Exploiting Instruction Correlation for Prefetching Irregular Memory Accesses
by: Li, Mengming, et al.
Published: (2026)

Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems
by: Ge, Mengke, et al.
Published: (2024)

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
by: Gao, Mingzhe, et al.
Published: (2024)

Voxel-CIM: An Efficient Compute-in-Memory Accelerator for Voxel-based Point Cloud Neural Networks
by: Lin, Xipeng, et al.
Published: (2024)

UpDown: Programmable fine-grained Events for Scalable Performance on Irregular Applications
by: Rajasukumar, Andronicus, et al.
Published: (2024)

M2XFP: A Metadata-Augmented Microscaling Data Format for Efficient Low-bit Quantization
by: Hu, Weiming, et al.
Published: (2026)

Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads
by: Popovici, Doru Thom, et al.
Published: (2025)

MoE-Hub: Taming Software Complexity for Seamless MoE Overlap with Hardware-Accelerated Communication on Multi-GPU Systems
by: Zhou, Zhuoshan, et al.
Published: (2026)

SCREME: A Scalable Framework for Resilient Memory Design
by: Li, Fan, et al.
Published: (2025)

CIMPool: Scalable Neural Network Acceleration for Compute-In-Memory using Weight Pools
by: Li, Shurui, et al.
Published: (2025)

Gaze into the Pattern: Characterizing Spatial Patterns with Internal Temporal Correlations for Hardware Prefetching
by: Chen, Zixiao, et al.
Published: (2024)

3D-TrIM: A Memory-Efficient Spatial Computing Architecture for Convolution Workloads
by: Sestito, Cristian, et al.
Published: (2025)

RT-NeRF: Real-Time On-Device Neural Radiance Fields Towards Immersive AR/VR Rendering
by: Li, Chaojian, et al.
Published: (2022)

Data-aware Dynamic Execution of Irregular Workloads on Heterogeneous Systems
by: Bai, Zhenyu, et al.
Published: (2025)

A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
by: Benz, Thomas, et al.
Published: (2025)

HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads
by: Negi, Shubham, et al.
Published: (2024)

Survey of Disaggregated Memory: Cross-layer Technique Insights for Next-Generation Datacenters
by: Wang, Jing, et al.
Published: (2025)

Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V Cores
by: Colagrande, Luca, et al.
Published: (2025)

Workload Characterization for Branch Predictability
by: Vikas, FNU, et al.
Published: (2025)

QED: Scalable Verification of Hardware Memory Consistency
by: Ravi, Gokulan, et al.
Published: (2024)

ChatHLS: Towards Systematic Design Automation and Optimization for High-Level Synthesis
by: Li, Runkai, et al.
Published: (2025)

RPCAcc: A High-Performance and Reconfigurable PCIe-attached RPC Accelerator
by: Zhang, Jie, et al.
Published: (2024)

PIM-malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures
by: Lee, Dongjae, et al.
Published: (2025)

A Hybrid-Domain Floating-Point Compute-in-Memory Architecture for Efficient Acceleration of High-Precision Deep Neural Networks
by: Yi, Zhiqiang, et al.
Published: (2025)

No One-Size-Fits-All: A Workload-Driven Characterization of Bit-Parallel vs. Bit-Serial Data Layouts for Processing-using-Memory
by: Zhang, Jingyao, et al.
Published: (2025)

SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices
by: Zhang, Yipu, et al.
Published: (2025)

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
by: Caon, Michele, et al.
Published: (2024)