GSIM: Accelerating RTL Simulation for Large-Scale Designs
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arXiv
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| Auteurs principaux: | , , , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866918113596932096 |
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| author | Chen, Lu Zhao, Dingyi Yu, Zihao Sun, Ninghui Bao, Yungang |
| author_facet | Chen, Lu Zhao, Dingyi Yu, Zihao Sun, Ninghui Bao, Yungang |
| contents | Register Transfer Level (RTL) simulation is widely used in design space exploration, verification, debugging, and preliminary performance evaluation for hardware design. Among various RTL simulation approaches, software simulation is the most commonly used due to its flexibility, low cost, and ease of debugging. However, the slow simulation of complex designs has become the bottleneck in design flow. In this work, we explore the sources of computation overhead of RTL simulation and conclude them into four factors. To optimize these factors, we propose several techniques at the supernode level, node level, and bit level. Finally, we implement these techniques in a novel RTL simulator GSIM. GSIM succeeds in simulating XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, GSIM can achieve speedup of 7.34x for booting Linux on XiangShan, and 19.94x for running CoreMark on Rocket. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_02236 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | GSIM: Accelerating RTL Simulation for Large-Scale Designs Chen, Lu Zhao, Dingyi Yu, Zihao Sun, Ninghui Bao, Yungang Hardware Architecture Register Transfer Level (RTL) simulation is widely used in design space exploration, verification, debugging, and preliminary performance evaluation for hardware design. Among various RTL simulation approaches, software simulation is the most commonly used due to its flexibility, low cost, and ease of debugging. However, the slow simulation of complex designs has become the bottleneck in design flow. In this work, we explore the sources of computation overhead of RTL simulation and conclude them into four factors. To optimize these factors, we propose several techniques at the supernode level, node level, and bit level. Finally, we implement these techniques in a novel RTL simulator GSIM. GSIM succeeds in simulating XiangShan, the state-of-the-art open-source RISC-V processor. Besides, compared to Verilator, GSIM can achieve speedup of 7.34x for booting Linux on XiangShan, and 19.94x for running CoreMark on Rocket. |
| title | GSIM: Accelerating RTL Simulation for Large-Scale Designs |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.02236 |