Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
Fuente:
arXiv
Saved in:
| Main Authors: | Zoni, Davide, Galimberti, Andrea, Guarisco, Adriano |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
by: Galimberti, Andrea, et al.
Published: (2024)
by: Galimberti, Andrea, et al.
Published: (2024)
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
by: Montanaro, Gabriele, et al.
Published: (2024)
by: Montanaro, Gabriele, et al.
Published: (2024)
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024)
by: Zoni, Davide, et al.
Published: (2024)
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs
by: Galli, Davide, et al.
Published: (2024)
by: Galli, Davide, et al.
Published: (2024)
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
by: Galimberti, Andrea, et al.
Published: (2025)
by: Galimberti, Andrea, et al.
Published: (2025)
Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)
by: Galimberti, Andrea, et al.
Published: (2024)
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)
by: Ye, Junhao, et al.
Published: (2026)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
Learning Cache Coherence Traffic for NoC Routing Design
by: Xiong, Guochu, et al.
Published: (2025)
by: Xiong, Guochu, et al.
Published: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)
by: Chen, Lu, et al.
Published: (2025)
MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
by: Chaurasia, Ansh
Published: (2025)
by: Chaurasia, Ansh
Published: (2025)
Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
by: Sehm, Robin, et al.
Published: (2025)
by: Sehm, Robin, et al.
Published: (2025)
UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)
by: Hu, Yuchen, et al.
Published: (2024)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)
by: Yin, Shuo, et al.
Published: (2026)
CHIMERA: A Flexible and Scalable 3.1 TOPS/W AI-MCU with Transformer Accelerator and 563 Gb/s Shared-L2 Memory Subsystem with QoS Guarantees
by: Leone, Lorenzo, et al.
Published: (2026)
by: Leone, Lorenzo, et al.
Published: (2026)
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
by: Chao, Zhiteng, et al.
Published: (2025)
by: Chao, Zhiteng, et al.
Published: (2025)
VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)
by: Qi, Haomin, et al.
Published: (2025)
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)
by: Qin, Kun, et al.
Published: (2025)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)
by: Allam, Ahmed, et al.
Published: (2024)
Exploring DRAM Cache Prefetching for Pooled Memory
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)
by: Tirumalasetty, Chandrahas, et al.
Published: (2024)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)
by: Krupp, Lukas, et al.
Published: (2026)
The Open-Source BlackParrot-BedRock Cache Coherence System
by: Wyse, Mark Unruh
Published: (2025)
by: Wyse, Mark Unruh
Published: (2025)
MARS: Processing-In-Memory Acceleration of Raw Signal Genome Analysis Inside the Storage Subsystem
by: Soysal, Melina, et al.
Published: (2025)
by: Soysal, Melina, et al.
Published: (2025)
Improving the Representativeness of Simulation Intervals for the Cache Memory System
by: Bueno, Nicolas, et al.
Published: (2024)
by: Bueno, Nicolas, et al.
Published: (2024)
Automated Multi-Agent Workflows for RTL Design
by: Bhattaram, Amulya, et al.
Published: (2025)
by: Bhattaram, Amulya, et al.
Published: (2025)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
by: Zhou, Jie, et al.
Published: (2025)
by: Zhou, Jie, et al.
Published: (2025)
CMD: A Cache-assisted GPU Memory Deduplication Architecture
by: Zhao, Wei, et al.
Published: (2024)
by: Zhao, Wei, et al.
Published: (2024)
Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory
by: Hong, Jeongmin, et al.
Published: (2024)
by: Hong, Jeongmin, et al.
Published: (2024)
Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
Fast-OverlaPIM: A Fast Overlap-driven Mapping Framework for Processing In-Memory Neural Network Acceleration
by: Wang, Xuan, et al.
Published: (2024)
by: Wang, Xuan, et al.
Published: (2024)
Area-Efficient In-Memory Computing for Mixture-of-Experts via Multiplexing and Caching
by: Gao, Hanyuan, et al.
Published: (2026)
by: Gao, Hanyuan, et al.
Published: (2026)
SCREME: A Scalable Framework for Resilient Memory Design
by: Li, Fan, et al.
Published: (2025)
by: Li, Fan, et al.
Published: (2025)
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)
by: Li, Chengxi, et al.
Published: (2025)
RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)
by: Tan, Qinhan, et al.
Published: (2024)
ROVER: RTL Optimization via Verified E-Graph Rewriting
by: Coward, Samuel, et al.
Published: (2024)
by: Coward, Samuel, et al.
Published: (2024)
Assessing Large Language Models in Generating RTL Design Specifications
by: Huang, Hung-Ming, et al.
Published: (2025)
by: Huang, Hung-Ming, et al.
Published: (2025)
Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)
by: Ifrim, Rares, et al.
Published: (2025)
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
by: Tsai, Yun-Da, et al.
Published: (2023)
by: Tsai, Yun-Da, et al.
Published: (2023)
Similar Items
-
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms
by: Galimberti, Andrea, et al.
Published: (2024) -
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
by: Montanaro, Gabriele, et al.
Published: (2024) -
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
by: Zoni, Davide, et al.
Published: (2024) -
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs
by: Galli, Davide, et al.
Published: (2024) -
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs
by: Galimberti, Andrea, et al.
Published: (2025)