OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866917080493719552 |
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| author | Shen, Shan Li, Xingyang Liu, Zhuohua Ma, Junhao Wang, Yikai Wu, Yiheng Sun, Yuquan Xing, Wei W. |
| author_facet | Shen, Shan Li, Xingyang Liu, Zhuohua Ma, Junhao Wang, Yikai Wu, Yiheng Sun, Yuquan Xing, Wei W. |
| contents | Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheral-circuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higher-fidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at https://github.com/ShenShan123/OpenYield |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_04106 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite Shen, Shan Li, Xingyang Liu, Zhuohua Ma, Junhao Wang, Yikai Wu, Yiheng Sun, Yuquan Xing, Wei W. Hardware Architecture Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheral-circuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higher-fidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at https://github.com/ShenShan123/OpenYield |
| title | OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.04106 |