:: Library Catalog

Cover Image

Saved in:

Bibliographic Details
Main Authors:	Purini, Suresh, Garg, Siddhant, Gaur, Mudit, Bhat, Sankalp, Mupparapu, Sohan, Ravindran, Arun
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	https://arxiv.org/abs/2508.06047
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)

AiEDA: Agentic AI Design Framework for Digital ASIC System Design
by: Patra, Aditya, et al.
Published: (2024)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
by: Wang, Yonghao, et al.
Published: (2026)

SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design
by: Alvanaki, Elisavet Lydia, et al.
Published: (2025)

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)

Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
by: Yu, Zhongzhi, et al.
Published: (2025)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)

RTL++: Graph-enhanced LLM for RTL Code Generation
by: Akyash, Mohammad, et al.
Published: (2025)

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols
by: Sheth, Arnav, et al.
Published: (2025)

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
by: Li, Jintao, et al.
Published: (2024)

Preemption-Enhanced Benchmark Suite for FPGAs
by: Malik, Arsalan Ali, et al.
Published: (2025)

OpenYield: An Open-Source SRAM Yield Analysis and Optimization Benchmark Suite
by: Shen, Shan, et al.
Published: (2025)

CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
by: Shi, Zhengyuan, et al.
Published: (2026)

Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)

GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization
by: Wang, Yiting, et al.
Published: (2025)

LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
by: Maddala, Karthik, et al.
Published: (2024)

ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)

OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
by: Sarkar, Rishov, et al.
Published: (2025)

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)

RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)

Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
by: Sehm, Robin, et al.
Published: (2025)

ROVER: RTL Optimization via Verified E-Graph Rewriting
by: Coward, Samuel, et al.
Published: (2024)

UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
by: DeLorenzo, Matthew, et al.
Published: (2024)

Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)

RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
by: Tsai, Yun-Da, et al.
Published: (2023)

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
by: Emami, Mahyar, et al.
Published: (2023)

ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)

Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)

POET: Power-Oriented Evolutionary Tuning for LLM-Based RTL PPA Optimization
by: Ping, Heng, et al.
Published: (2026)

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
by: Ye, Junhao, et al.
Published: (2025)

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
by: Bhandari, Jitendra, et al.
Published: (2024)

HYPERHEURIST: A Simulated Annealing-Based Control Framework for LLM-Driven Code Generation in Optimized Hardware Design
by: Ahir, Shiva, et al.
Published: (2026)

ForgeBench: A Machine Learning Benchmark Suite and Auto-Generation Framework for Next-Generation HLS Tools
by: Wanna, Andy, et al.
Published: (2025)

MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
by: Chaurasia, Ansh
Published: (2025)

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)

FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)