Recurrent Deep Differentiable Logic Gate Networks
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
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| _version_ | 1866908482208268288 |
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| author | Bührer, Simon Plesner, Andreas Aczel, Till Wattenhofer, Roger |
| author_facet | Bührer, Simon Plesner, Andreas Aczel, Till Wattenhofer, Roger |
| contents | While differentiable logic gates have shown promise in feedforward networks, their application to sequential modeling remains unexplored. This paper presents the first implementation of Recurrent Deep Differentiable Logic Gate Networks (RDDLGN), combining Boolean operations with recurrent architectures for sequence-to-sequence learning.
Evaluated on WMT'14 English-German translation, RDDLGN achieves 5.00 BLEU and 30.9\% accuracy during training, approaching GRU performance (5.41 BLEU) and graceful degradation (4.39 BLEU) during inference. This work establishes recurrent logic-based neural computation as viable, opening research directions for FPGA acceleration in sequential modeling and other recursive network architectures. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_06097 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Recurrent Deep Differentiable Logic Gate Networks Bührer, Simon Plesner, Andreas Aczel, Till Wattenhofer, Roger Machine Learning While differentiable logic gates have shown promise in feedforward networks, their application to sequential modeling remains unexplored. This paper presents the first implementation of Recurrent Deep Differentiable Logic Gate Networks (RDDLGN), combining Boolean operations with recurrent architectures for sequence-to-sequence learning. Evaluated on WMT'14 English-German translation, RDDLGN achieves 5.00 BLEU and 30.9\% accuracy during training, approaching GRU performance (5.41 BLEU) and graceful degradation (4.39 BLEU) during inference. This work establishes recurrent logic-based neural computation as viable, opening research directions for FPGA acceleration in sequential modeling and other recursive network architectures. |
| title | Recurrent Deep Differentiable Logic Gate Networks |
| topic | Machine Learning |
| url | https://arxiv.org/abs/2508.06097 |