Nail: Not Another Fault-Injection Framework for Chisel-generated RTL
Fuente:
arXiv
Saved in:
| Main Authors: | Sehm, Robin, Ewert, Christian, Buchty, Rainer, Berekovic, Mladen, Mulhem, Saleh |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
Lightweight Unified Sha-3/Shake Architecture with a Fault-Resilient State
by: Ewert, Christian, et al.
Published: (2025)
by: Ewert, Christian, et al.
Published: (2025)
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024)
by: Mulhem, Saleh, et al.
Published: (2024)
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
by: Nešković, Andrija, et al.
Published: (2023)
by: Nešković, Andrija, et al.
Published: (2023)
SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security
by: Ewert, Christian, et al.
Published: (2026)
by: Ewert, Christian, et al.
Published: (2026)
IMS: Intelligent Hardware Monitoring System for Secure SoCs
by: Foudhaili, Wadid, et al.
Published: (2026)
by: Foudhaili, Wadid, et al.
Published: (2026)
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach
by: Foudhaili, Wadid, et al.
Published: (2024)
by: Foudhaili, Wadid, et al.
Published: (2024)
Robust Beam Codebooks for mmWave/THz Systems: Toward a Stochastic RL Approach
by: Nechi, Anouar, et al.
Published: (2026)
by: Nechi, Anouar, et al.
Published: (2026)
MemorySim: An RTL-level, timing accurate simulator model for the Chisel ecosystem
by: Chaurasia, Ansh
Published: (2025)
by: Chaurasia, Ansh
Published: (2025)
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
by: Niu, Juxin, et al.
Published: (2025)
by: Niu, Juxin, et al.
Published: (2025)
Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
Tywaves: A Typed Waveform Viewer for Chisel
by: Meloni, Raffaele, et al.
Published: (2024)
by: Meloni, Raffaele, et al.
Published: (2024)
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
UVLLM: An Automated Universal RTL Verification Framework using LLMs
by: Hu, Yuchen, et al.
Published: (2024)
by: Hu, Yuchen, et al.
Published: (2024)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)
by: Yin, Shuo, et al.
Published: (2026)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)
by: Qi, Haomin, et al.
Published: (2025)
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)
by: Qin, Kun, et al.
Published: (2025)
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems
by: Zoni, Davide, et al.
Published: (2025)
by: Zoni, Davide, et al.
Published: (2025)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
by: Masar, Filip, et al.
Published: (2025)
by: Masar, Filip, et al.
Published: (2025)
Fault Injection in On-Chip Interconnects: A Comparative Study of Wishbone, AXI-Lite, and AXI
by: Zhao, Hongwei, et al.
Published: (2025)
by: Zhao, Hongwei, et al.
Published: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)
by: Chen, Lu, et al.
Published: (2025)
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)
by: Li, Chengxi, et al.
Published: (2025)
RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)
by: Tan, Qinhan, et al.
Published: (2024)
ROVER: RTL Optimization via Verified E-Graph Rewriting
by: Coward, Samuel, et al.
Published: (2024)
by: Coward, Samuel, et al.
Published: (2024)
FsimNNs: An Open-Source Graph Neural Network Platform for SEU Simulation-based Fault Injection
by: Lu, Li, et al.
Published: (2025)
by: Lu, Li, et al.
Published: (2025)
Analyzing the capabilities of HLS and RTL tools in the design of an FPGA Montgomery Multiplier
by: Ifrim, Rares, et al.
Published: (2025)
by: Ifrim, Rares, et al.
Published: (2025)
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models
by: Tsai, Yun-Da, et al.
Published: (2023)
by: Tsai, Yun-Da, et al.
Published: (2023)
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
by: Emami, Mahyar, et al.
Published: (2023)
by: Emami, Mahyar, et al.
Published: (2023)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)
by: Deng, Chenhui, et al.
Published: (2026)
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
by: Chao, Zhiteng, et al.
Published: (2025)
by: Chao, Zhiteng, et al.
Published: (2025)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)
by: Allam, Ahmed, et al.
Published: (2024)
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)
by: Fang, Wenji, et al.
Published: (2026)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)
by: Krupp, Lukas, et al.
Published: (2026)
DecoRTL: A Run-time Decoding Framework for RTL Code Generation with LLMs
by: Akyash, Mohammad, et al.
Published: (2025)
by: Akyash, Mohammad, et al.
Published: (2025)
QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
by: Reimann, Lennart M., et al.
Published: (2024)
by: Reimann, Lennart M., et al.
Published: (2024)
ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis
by: Purini, Suresh, et al.
Published: (2025)
by: Purini, Suresh, et al.
Published: (2025)
RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)
by: Zhu, Yan, et al.
Published: (2026)
by: Zhu, Yan, et al.
Published: (2026)
Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation
by: Wang, Runxi, et al.
Published: (2024)
by: Wang, Runxi, et al.
Published: (2024)
Similar Items
-
Lightweight Unified Sha-3/Shake Architecture with a Fault-Resilient State
by: Ewert, Christian, et al.
Published: (2025) -
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
by: Mulhem, Saleh, et al.
Published: (2024) -
SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?
by: Nešković, Andrija, et al.
Published: (2023) -
SAILOR: A Scalable and Energy-Efficient Ultra-Lightweight RISC-V for IoT Security
by: Ewert, Christian, et al.
Published: (2026) -
IMS: Intelligent Hardware Monitoring System for Secure SoCs
by: Foudhaili, Wadid, et al.
Published: (2026)