Saved in:
| Main Authors: | , , , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2508.07110 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866918121006170112 |
|---|---|
| author | Ruotolo, Lorenzo Orlandic, Lara Yu, Pengbo Brunion, Moritz Pagliari, Daniele Jahier Biswas, Dwaipayan Ansaloni, Giovanni Atienza, David Ryckaert, Julien Catthoor, Francky Chen, Yukai |
| author_facet | Ruotolo, Lorenzo Orlandic, Lara Yu, Pengbo Brunion, Moritz Pagliari, Daniele Jahier Biswas, Dwaipayan Ansaloni, Giovanni Atienza, David Ryckaert, Julien Catthoor, Francky Chen, Yukai |
| contents | This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect efficiency in advanced Angstrom-era technologies. The design emphasizes reduced wire length and high core density by utilizing specialized memory structures and SIMD (Single Instruction, Multiple Data) units. Five configurations are synthesized and evaluated using the IMEC A10 nanosheet node PDK. Key physical design metrics are compared across configurations and against VWR2A, a state-of-the-art (SoA) DSIP baseline. Results show that our architecture achieves over 2x lower normalized wire length and more than 3x higher density than the SoA, with low variability in the metrics across all configurations, making it a promising solution for next-generation DSIP designs. These improvements are achieved with minimal manual layout intervention, demonstrating the architecture's intrinsic physical efficiency and potential for low-cost wire-friendly implementation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_07110 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes Ruotolo, Lorenzo Orlandic, Lara Yu, Pengbo Brunion, Moritz Pagliari, Daniele Jahier Biswas, Dwaipayan Ansaloni, Giovanni Atienza, David Ryckaert, Julien Catthoor, Francky Chen, Yukai Hardware Architecture This paper presents the physical design exploration of a domain-specific processor (DSIP) architecture targeted at machine learning (ML), addressing the challenges of interconnect efficiency in advanced Angstrom-era technologies. The design emphasizes reduced wire length and high core density by utilizing specialized memory structures and SIMD (Single Instruction, Multiple Data) units. Five configurations are synthesized and evaluated using the IMEC A10 nanosheet node PDK. Key physical design metrics are compared across configurations and against VWR2A, a state-of-the-art (SoA) DSIP baseline. Results show that our architecture achieves over 2x lower normalized wire length and more than 3x higher density than the SoA, with low variability in the metrics across all configurations, making it a promising solution for next-generation DSIP designs. These improvements are achieved with minimal manual layout intervention, demonstrating the architecture's intrinsic physical efficiency and potential for low-cost wire-friendly implementation. |
| title | Physical Design Exploration of a Wire-Friendly Domain-Specific Processor for Angstrom-Era Nodes |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.07110 |