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| Auteurs principaux: | , , |
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| Format: | Preprint |
| Publié: |
2025
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| Sujets: | |
| Accès en ligne: | https://arxiv.org/abs/2508.08425 |
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| _version_ | 1866916984329863168 |
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| author | Jalaleddine, Marwan Li, Jiajie Gross, Warren J. |
| author_facet | Jalaleddine, Marwan Li, Jiajie Gross, Warren J. |
| contents | To extend the applications of polar codes within next-generation wireless communication systems, it is essential to incorporate support for Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ) schemes. The baseline IR-HARQ scheme's reliance on set-based operations leads to irregular memory access patterns, posing significant challenges for efficient hardware implementation. Furthermore, the introduction of new bit types increases the number of fast nodes that are decoded without traversing the sub-tree, resulting in a substantial area overhead when implemented in hardware. To address these issues and improve hardware compatibility, we propose transforming the set-based operations within the polar IR-HARQ scheme into binary vector operations. Additionally, we introduce a new fast node integration approach that avoids increasing the number of fast nodes, thereby minimizing the associated area overhead. Our proposed scheme results in a memory overhead of 25-27% compared to successive cancellation list (SCL) decoding without IR-HARQ support. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_08425 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Hardware-friendly IR-HARQ for Polar SCL Decoders Jalaleddine, Marwan Li, Jiajie Gross, Warren J. Signal Processing To extend the applications of polar codes within next-generation wireless communication systems, it is essential to incorporate support for Incremental Redundancy (IR) Hybrid Automatic Repeat Request (HARQ) schemes. The baseline IR-HARQ scheme's reliance on set-based operations leads to irregular memory access patterns, posing significant challenges for efficient hardware implementation. Furthermore, the introduction of new bit types increases the number of fast nodes that are decoded without traversing the sub-tree, resulting in a substantial area overhead when implemented in hardware. To address these issues and improve hardware compatibility, we propose transforming the set-based operations within the polar IR-HARQ scheme into binary vector operations. Additionally, we introduce a new fast node integration approach that avoids increasing the number of fast nodes, thereby minimizing the associated area overhead. Our proposed scheme results in a memory overhead of 25-27% compared to successive cancellation list (SCL) decoding without IR-HARQ support. |
| title | Hardware-friendly IR-HARQ for Polar SCL Decoders |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2508.08425 |