Architecture and FPGA Implementation of Digital Time-to-Digital Converter for Sensing Applications
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866911102409900032 |
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| author | Hijazi, Zeinab Bzeih, Fatima Ibrahim, Ali |
| author_facet | Hijazi, Zeinab Bzeih, Fatima Ibrahim, Ali |
| contents | Many application domains face the challenges of high-power consumption and high computational demands, especially with the advancement in embedded machine learning and edge computing. Designing application-specific circuits is crucial to reducing hardware complexity and power consumption. In these perspectives, this paper presents the design of a Digital Time-to-Digital converter (DTDC) based on multiple delay line topologies. The DTDC is implemented in VHDL for the Xilinx Artix-7 AC701 FPGA device. Simulation results demonstrate the effectiveness of the circuit in converting the input period along a wide range up to 1ps. The designed circuit is implemented with less than 1% of the resource utilization on the target FPGA device. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_08725 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Architecture and FPGA Implementation of Digital Time-to-Digital Converter for Sensing Applications Hijazi, Zeinab Bzeih, Fatima Ibrahim, Ali Systems and Control Many application domains face the challenges of high-power consumption and high computational demands, especially with the advancement in embedded machine learning and edge computing. Designing application-specific circuits is crucial to reducing hardware complexity and power consumption. In these perspectives, this paper presents the design of a Digital Time-to-Digital converter (DTDC) based on multiple delay line topologies. The DTDC is implemented in VHDL for the Xilinx Artix-7 AC701 FPGA device. Simulation results demonstrate the effectiveness of the circuit in converting the input period along a wide range up to 1ps. The designed circuit is implemented with less than 1% of the resource utilization on the target FPGA device. |
| title | Architecture and FPGA Implementation of Digital Time-to-Digital Converter for Sensing Applications |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2508.08725 |