A 28nm Multiply-Accumulate ASIC Architecture for On-Chip Data Compression in MHz Frame Rate X-ray and Electron Pixel Detectors

Fuente: arXiv

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Bibliographic Details
Main Authors:	Rasheedi, Rami, Contini, Nicholas, Gharib, Mohamed Adel, Strempfer, Sebastian, Gnanasekaran, Senthil, Abdelzaher, Salma, Guruswamy, Tejas, Yoshii, Kazutomo, Hammer, Mike, Shi, Henry, Chen, Yu-Sheng, Rota, Lorenzo, Doering, Dionisio, Dragone, Angelo, Zhou, Tao, Miceli, Antonino
Format:	Preprint
Published:	2025
Subjects:	Instrumentation and Detectors
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

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