A Limits Study of Memory-side Tiering Telemetry
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arXiv
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| Auteurs principaux: | , , |
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| Format: | Preprint |
| Publié: |
2025
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| _version_ | 1866909735616249856 |
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| author | Petrucci, Vinicius Zacarias, Felippe Roberts, David |
| author_facet | Petrucci, Vinicius Zacarias, Felippe Roberts, David |
| contents | Increasing workload demands and emerging technologies necessitate the use of various memory and storage tiers in computing systems. This paper presents results from a CXL-based Experimental Memory Request Logger that reveals precise memory access patterns at runtime without interfering with the running workloads. We use it for software emulation of future memory telemetry hardware. By combining reactive placement based on data address monitoring, proactive data movement, and compiler hints, a Hotness Monitoring Unit (HMU) within memory modules can greatly improve memory tiering solutions. Analysis of page placement using profiled access counts on a Deep Learning Recommendation Model (DLRM) indicates a potential 1.94x speedup over Linux NUMA balancing tiering, and only a 3% slowdown compared to Host-DRAM allocation while offloading over 90% of pages to CXL memory. The study underscores the limitations of existing tiering strategies in terms of coverage and accuracy, and makes a strong case for programmable, device-level telemetry as a scalable and efficient solution for future memory systems. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_09351 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Limits Study of Memory-side Tiering Telemetry Petrucci, Vinicius Zacarias, Felippe Roberts, David Operating Systems Hardware Architecture Performance Increasing workload demands and emerging technologies necessitate the use of various memory and storage tiers in computing systems. This paper presents results from a CXL-based Experimental Memory Request Logger that reveals precise memory access patterns at runtime without interfering with the running workloads. We use it for software emulation of future memory telemetry hardware. By combining reactive placement based on data address monitoring, proactive data movement, and compiler hints, a Hotness Monitoring Unit (HMU) within memory modules can greatly improve memory tiering solutions. Analysis of page placement using profiled access counts on a Deep Learning Recommendation Model (DLRM) indicates a potential 1.94x speedup over Linux NUMA balancing tiering, and only a 3% slowdown compared to Host-DRAM allocation while offloading over 90% of pages to CXL memory. The study underscores the limitations of existing tiering strategies in terms of coverage and accuracy, and makes a strong case for programmable, device-level telemetry as a scalable and efficient solution for future memory systems. |
| title | A Limits Study of Memory-side Tiering Telemetry |
| topic | Operating Systems Hardware Architecture Performance |
| url | https://arxiv.org/abs/2508.09351 |