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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2508.10283 |
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| _version_ | 1866908489825124352 |
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| author | Wang, Zekun Yue, Binghao Pan, Weitao Shi, Jiangyi Hao, Yue |
| author_facet | Wang, Zekun Yue, Binghao Pan, Weitao Shi, Jiangyi Hao, Yue |
| contents | Large-scale timers are ubiquitous in network processing, including flow table entry expiration control in software defined network (SDN) switches, MAC address aging in Ethernet bridges, and retransmission timeout management in TCP/IP protocols. Conventional implementations suffer from critical limitations: low timing accuracy due to large-scale timer traversal and high computational overhead for new timer insertion. This paper presents a hybrid-architecture hardware priority queue based on systolic arrays and shift registers for efficient timer queue management. The design uniquely supports five operations: enqueue, dequeue, delete, update, and peek.To the best of our knowledge, it is the first hardware priority queue enabling in-queue priority updates. By leveraging centralized Boolean logic encoding within systolic blocks, the design efficiently generates set/shift control signals while the novel push-first operation ensures FIFO ordering for same-priority timers without additional metadata. Experimental results demonstrate that the design operates at over 400 MHz on FPGAs, achieving a 2.2-2.8x reduction in resource consumption compared to state-of-the-art implementations. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_10283 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Design of a Timer Queue Supporting Dynamic Update Operations Wang, Zekun Yue, Binghao Pan, Weitao Shi, Jiangyi Hao, Yue Networking and Internet Architecture Large-scale timers are ubiquitous in network processing, including flow table entry expiration control in software defined network (SDN) switches, MAC address aging in Ethernet bridges, and retransmission timeout management in TCP/IP protocols. Conventional implementations suffer from critical limitations: low timing accuracy due to large-scale timer traversal and high computational overhead for new timer insertion. This paper presents a hybrid-architecture hardware priority queue based on systolic arrays and shift registers for efficient timer queue management. The design uniquely supports five operations: enqueue, dequeue, delete, update, and peek.To the best of our knowledge, it is the first hardware priority queue enabling in-queue priority updates. By leveraging centralized Boolean logic encoding within systolic blocks, the design efficiently generates set/shift control signals while the novel push-first operation ensures FIFO ordering for same-priority timers without additional metadata. Experimental results demonstrate that the design operates at over 400 MHz on FPGAs, achieving a 2.2-2.8x reduction in resource consumption compared to state-of-the-art implementations. |
| title | Design of a Timer Queue Supporting Dynamic Update Operations |
| topic | Networking and Internet Architecture |
| url | https://arxiv.org/abs/2508.10283 |