A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866908492680396800 |
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| author | Zhou, Wenyong Ren, Yuan Zhou, Jiajun Hou, Tianshu Wong, Ngai |
| author_facet | Zhou, Wenyong Ren, Yuan Zhou, Jiajun Hou, Tianshu Wong, Ngai |
| contents | Designing lightweight convolutional neural network (CNN) models is an active research area in edge AI. Compute-in-memory (CIM) provides a new computing paradigm to alleviate time and energy consumption caused by data transfer in von Neumann architecture. Among competing alternatives, resistive random-access memory (RRAM) is a promising CIM device owing to its reliability and multi-bit programmability. However, classical lightweight designs such as depthwise convolution incurs under-utilization of RRAM crossbars restricted by their inherently dense weight-to-RRAM cell mapping. To build an RRAM-friendly yet efficient CNN, we evaluate the hardware cost of DenseNet which maintains a high accuracy vs other CNNs at a small parameter count. Observing the linearly increasing channels in DenseNet leads to a low crossbar utilization and causes large latency and energy consumption, we propose a scheme that concatenates feature maps of front layers to form the input of the last layer in each stage. Experiments show that our proposed model consumes less time and energy than conventional ResNet and DenseNet, while producing competitive accuracy on CIFAR and ImageNet datasets. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_12251 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips Zhou, Wenyong Ren, Yuan Zhou, Jiajun Hou, Tianshu Wong, Ngai Hardware Architecture Designing lightweight convolutional neural network (CNN) models is an active research area in edge AI. Compute-in-memory (CIM) provides a new computing paradigm to alleviate time and energy consumption caused by data transfer in von Neumann architecture. Among competing alternatives, resistive random-access memory (RRAM) is a promising CIM device owing to its reliability and multi-bit programmability. However, classical lightweight designs such as depthwise convolution incurs under-utilization of RRAM crossbars restricted by their inherently dense weight-to-RRAM cell mapping. To build an RRAM-friendly yet efficient CNN, we evaluate the hardware cost of DenseNet which maintains a high accuracy vs other CNNs at a small parameter count. Observing the linearly increasing channels in DenseNet leads to a low crossbar utilization and causes large latency and energy consumption, we propose a scheme that concatenates feature maps of front layers to form the input of the last layer in each stage. Experiments show that our proposed model consumes less time and energy than conventional ResNet and DenseNet, while producing competitive accuracy on CIFAR and ImageNet datasets. |
| title | A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.12251 |