Soft Error Probability Estimation of Nano-scale Combinational Circuits
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arXiv
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| Main Authors: | , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866912541042540544 |
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| author | Jockar, Ali Raji, Mohsen |
| author_facet | Jockar, Ali Raji, Mohsen |
| contents | As technology scales, nano-scale digital circuits face heightened susceptibility to single event upsets (SEUs) and transients (SETs) due to shrinking feature sizes and reduced operating voltages. While logical, electrical, and timing masking effects influence soft error probability (SEP), the combined impact of process variation (PV) and aging-induced degradation further complicates SEP estimation. Existing approaches often address PV or aging in isolation, or rely on computationally intensive methods like Monte Carlo simulations, limiting their practicality for large-scale circuit optimization. This paper introduces a novel framework for SEP analysis that holistically integrates PV and aging effects. We propose an enhanced electrical masking model and a statistical methodology to quantify soft error probability under process and aging variations. Experimental results demonstrate that the proposed approach achieves high accuracy while reducing computational overhead by approximately 2.5% compared to Monte Carlo-based methods. This work advances the design of reliable nano-scale circuits by enabling efficient, accurate SEP estimation in the presence of manufacturing variability and long-term transistor degradation. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_12345 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Soft Error Probability Estimation of Nano-scale Combinational Circuits Jockar, Ali Raji, Mohsen Hardware Architecture As technology scales, nano-scale digital circuits face heightened susceptibility to single event upsets (SEUs) and transients (SETs) due to shrinking feature sizes and reduced operating voltages. While logical, electrical, and timing masking effects influence soft error probability (SEP), the combined impact of process variation (PV) and aging-induced degradation further complicates SEP estimation. Existing approaches often address PV or aging in isolation, or rely on computationally intensive methods like Monte Carlo simulations, limiting their practicality for large-scale circuit optimization. This paper introduces a novel framework for SEP analysis that holistically integrates PV and aging effects. We propose an enhanced electrical masking model and a statistical methodology to quantify soft error probability under process and aging variations. Experimental results demonstrate that the proposed approach achieves high accuracy while reducing computational overhead by approximately 2.5% compared to Monte Carlo-based methods. This work advances the design of reliable nano-scale circuits by enabling efficient, accurate SEP estimation in the presence of manufacturing variability and long-term transistor degradation. |
| title | Soft Error Probability Estimation of Nano-scale Combinational Circuits |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.12345 |