EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code

Fuente: arXiv

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Bibliographic Details
Main Authors:	Guo, Ping, Wang, Yiting, Ye, Wanghao, He, Yexiao, Wang, Ziyao, Dai, Xiaopeng, Li, Ang, Zhang, Qingfu
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture Artificial Intelligence
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2508.13156