Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures
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arXiv
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| Hauptverfasser: | , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| _version_ | 1866916905908961280 |
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| author | Tang, Ruibai Zhao, Wenlai |
| author_facet | Tang, Ruibai Zhao, Wenlai |
| contents | Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structures account for an average of 6.34\% (up to 12\%) of the total nodes in the benchmark circuits. Experimental results demonstrate that our methods yields an average performance improvement of 8.8\% (up to 22\%) on simulating benchmark circuits which include a variety of functional modules such as ALUs, adders, multipliers, SEC/DED checkers, and interrupt controllers, with only 0.7\% relative error. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_13159 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures Tang, Ruibai Zhao, Wenlai Hardware Architecture Performance Transistor-level simulation plays a vital role in validating the physical correctness of integrated circuits. However, such simulations are computationally expensive. This paper proposes three novel reduction methods specifically tailored to RC long-chain structures with different scales of time constant. Such structures account for an average of 6.34\% (up to 12\%) of the total nodes in the benchmark circuits. Experimental results demonstrate that our methods yields an average performance improvement of 8.8\% (up to 22\%) on simulating benchmark circuits which include a variety of functional modules such as ALUs, adders, multipliers, SEC/DED checkers, and interrupt controllers, with only 0.7\% relative error. |
| title | Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures |
| topic | Hardware Architecture Performance |
| url | https://arxiv.org/abs/2508.13159 |