Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866912541669588992 |
|---|---|
| author | Chen, Yibo Kurshan, Eren Motschman, Dave Johnson, Charles Xie, Yuan |
| author_facet | Chen, Yibo Kurshan, Eren Motschman, Dave Johnson, Charles Xie, Yuan |
| contents | 3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in μm range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_13160 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits Chen, Yibo Kurshan, Eren Motschman, Dave Johnson, Charles Xie, Yuan Hardware Architecture Emerging Technologies 3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for signal bus connections between layers) because the TSV size and pitch continue to scale in μm range and the metal to insulator ratio becomes smaller. Consequently, dense TSV farms can create lateral thermal blockages in thinned silicon substrate and exacerbate the local hotspots. In this paper, we propose a thermal-aware via farm placement technique for 3-D ICs to minimize lateral heat blockages caused by dense signal bus TSV structures. |
| title | Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits |
| topic | Hardware Architecture Emerging Technologies |
| url | https://arxiv.org/abs/2508.13160 |