Piano: A Multi-Constraint Pin Assignment-Aware Floorplanner
Fuente:
arXiv
Guardado en:
| Autores principales: | Xu, Zhexuan, Zhou, Kexin, Wang, Jie, Geng, Zijie, Xu, Siyuan, Kai, Shixiong, Yuan, Mingxuan, Wu, Feng |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
Ejemplares similares
Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
por: Wang, Zhihai, et al.
Publicado: (2024)
por: Wang, Zhihai, et al.
Publicado: (2024)
Timing-Driven Global Placement by Efficient Critical Path Extraction
por: Shi, Yunqi, et al.
Publicado: (2025)
por: Shi, Yunqi, et al.
Publicado: (2025)
One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner
por: Xu, Zhexuan, et al.
Publicado: (2025)
por: Xu, Zhexuan, et al.
Publicado: (2025)
LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
por: Zhong, Ruizhe, et al.
Publicado: (2023)
por: Zhong, Ruizhe, et al.
Publicado: (2023)
Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation
por: Shi, Yunqi, et al.
Publicado: (2025)
por: Shi, Yunqi, et al.
Publicado: (2025)
Thermal-Aware Floorplanner for 3D IC, including TSVs, Liquid Microchannels and Thermal Domains Optimization
por: Cuesta, David, et al.
Publicado: (2024)
por: Cuesta, David, et al.
Publicado: (2024)
FlowPlace: Flow Matching for Chip Placement
por: Xie, Peng, et al.
Publicado: (2026)
por: Xie, Peng, et al.
Publicado: (2026)
Efficient LLM inference solution on Intel GPU
por: Wu, Hui, et al.
Publicado: (2023)
por: Wu, Hui, et al.
Publicado: (2023)
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence
por: Qin, Haiyan, et al.
Publicado: (2025)
por: Qin, Haiyan, et al.
Publicado: (2025)
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
por: Ye, Junhao, et al.
Publicado: (2025)
por: Ye, Junhao, et al.
Publicado: (2025)
AnalogSeeker: An Open-source Foundation Language Model for Analog Circuit Design
por: Chen, Zihao, et al.
Publicado: (2025)
por: Chen, Zihao, et al.
Publicado: (2025)
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
por: Yao, Xufeng, et al.
Publicado: (2024)
por: Yao, Xufeng, et al.
Publicado: (2024)
CktEvo: Repository-Level RTL Code Benchmark for Design Evolution
por: Shi, Zhengyuan, et al.
Publicado: (2026)
por: Shi, Zhengyuan, et al.
Publicado: (2026)
Monitor Placement for Fault Localization in Deep Neural Network Accelerators
por: Liu, Wei-Kai
Publicado: (2023)
por: Liu, Wei-Kai
Publicado: (2023)
MARCA: Mamba Accelerator with ReConfigurable Architecture
por: Li, Jinhao, et al.
Publicado: (2024)
por: Li, Jinhao, et al.
Publicado: (2024)
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
por: Wang, Ning, et al.
Publicado: (2024)
por: Wang, Ning, et al.
Publicado: (2024)
EDA-Aware RTL Generation with Large Language Models
por: Islam, Mubashir ul, et al.
Publicado: (2024)
por: Islam, Mubashir ul, et al.
Publicado: (2024)
HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
por: Meng, Chang-Chih, et al.
Publicado: (2026)
por: Meng, Chang-Chih, et al.
Publicado: (2026)
ELSA: An ELastic SNN Inference Architecture for Efficient Neuromorphic Computing
por: You, Kang, et al.
Publicado: (2026)
por: You, Kang, et al.
Publicado: (2026)
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
por: Wang, Ning, et al.
Publicado: (2025)
por: Wang, Ning, et al.
Publicado: (2025)
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
por: Yao, Bingkun, et al.
Publicado: (2024)
por: Yao, Bingkun, et al.
Publicado: (2024)
A CMOS Probabilistic Computing Chip With In-situ hardware Aware Learning
por: Jhonsa, Jinesh, et al.
Publicado: (2025)
por: Jhonsa, Jinesh, et al.
Publicado: (2025)
Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead
por: Yang, Guang, et al.
Publicado: (2025)
por: Yang, Guang, et al.
Publicado: (2025)
GenAI-Driven Approach to RISC-V Supply Chain Exploration
por: Petrovic, Nenad, et al.
Publicado: (2026)
por: Petrovic, Nenad, et al.
Publicado: (2026)
Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview
por: Aliyev, Ilkin, et al.
Publicado: (2024)
por: Aliyev, Ilkin, et al.
Publicado: (2024)
HAPM -- Hardware Aware Pruning Method for CNN hardware accelerators in resource constrained devices
por: Peccia, Federico Nicolas, et al.
Publicado: (2024)
por: Peccia, Federico Nicolas, et al.
Publicado: (2024)
Salca: A Sparsity-Aware Hardware Accelerator for Efficient Long-Context Attention Decoding
por: Fan, Wang, et al.
Publicado: (2026)
por: Fan, Wang, et al.
Publicado: (2026)
A Micro Architectural Events Aware Real-Time Embedded System Fault Injector
por: Magliano, Enrico, et al.
Publicado: (2024)
por: Magliano, Enrico, et al.
Publicado: (2024)
TransPlace: Transferable Circuit Global Placement via Graph Neural Network
por: Hou, Yunbo, et al.
Publicado: (2025)
por: Hou, Yunbo, et al.
Publicado: (2025)
ViTAD: Timing Violation-Aware Debugging of RTL Code using Large Language Models
por: Lv, Wenhao, et al.
Publicado: (2025)
por: Lv, Wenhao, et al.
Publicado: (2025)
LUMINA: LLM-Guided GPU Architecture Exploration via Bottleneck Analysis
por: Zhang, Tao, et al.
Publicado: (2026)
por: Zhang, Tao, et al.
Publicado: (2026)
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
por: Fu, Lik Tung, et al.
Publicado: (2026)
por: Fu, Lik Tung, et al.
Publicado: (2026)
Qute: Towards Quantum-Native Database
por: Chen, Muzhi, et al.
Publicado: (2026)
por: Chen, Muzhi, et al.
Publicado: (2026)
Idle is the New Sleep: Configuration-Aware Alternative to Powering Off FPGA-Based DL Accelerators During Inactivity
por: Qian, Chao, et al.
Publicado: (2024)
por: Qian, Chao, et al.
Publicado: (2024)
Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
por: Liu, Jiale, et al.
Publicado: (2026)
por: Liu, Jiale, et al.
Publicado: (2026)
MixPE: Quantization and Hardware Co-design for Efficient LLM Inference
por: Zhang, Yu, et al.
Publicado: (2024)
por: Zhang, Yu, et al.
Publicado: (2024)
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
por: Chang, Kaiyan, et al.
Publicado: (2024)
por: Chang, Kaiyan, et al.
Publicado: (2024)
ForgeHLS: A Large-Scale, Open-Source Dataset for High-Level Synthesis
por: Peng, Zedong, et al.
Publicado: (2025)
por: Peng, Zedong, et al.
Publicado: (2025)
BBOPlace-Bench: Benchmarking Black-Box Optimization for Chip Placement
por: Xue, Ke, et al.
Publicado: (2025)
por: Xue, Ke, et al.
Publicado: (2025)
Automated Multi-Agent Workflows for RTL Design
por: Bhattaram, Amulya, et al.
Publicado: (2025)
por: Bhattaram, Amulya, et al.
Publicado: (2025)
Ejemplares similares
-
Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms
por: Wang, Zhihai, et al.
Publicado: (2024) -
Timing-Driven Global Placement by Efficient Critical Path Extraction
por: Shi, Yunqi, et al.
Publicado: (2025) -
One Step Beyond: Feedthrough & Placement-Aware Rectilinear Floorplanner
por: Xu, Zhexuan, et al.
Publicado: (2025) -
LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
por: Zhong, Ruizhe, et al.
Publicado: (2023) -
Open3DBench: Open-Source Benchmark for 3D-IC Backend Implementation and PPA Evaluation
por: Shi, Yunqi, et al.
Publicado: (2025)