Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration
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arXiv
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| Main Authors: | Du, Shuting, Ibrahim, Mohamed, Wan, Zishen, Zheng, Luqi, Zhao, Boheng, Fan, Zhenkun, Liu, Che-Kai, Krishna, Tushar, Raychowdhury, Arijit, Li, Haitong |
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| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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