FPGA Design and Implementation of Fixed-Point Fast Divider Using Goldschmidt Division Algorithm and Mitchell Multiplication Algorithm
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arXiv
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| Natura: | Preprint |
| Pubblicazione: |
2025
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| _version_ | 1866916910501724160 |
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| author | Yang, Jinkun |
| author_facet | Yang, Jinkun |
| contents | This paper presents a variable bit-width fixed-point fast divider using Goldschmidt division algorithm and Mitchell multiplication algorithm. Described using Verilog HDL and implemented on a Xilinx XC7Z020-2CLG400I FPGA, the proposed divider achieves over 99% computational accuracy with a minimum latency of 99.1 ns, which is 31.7 ns faster than existing single-precision dividers. Compared with a Goldschmidt divider using a Vedic multiplier, the proposed design reduces Slice Registers by 46.68%, Slice LUTs by 4.93%, and Slices by 11.85%, with less than 1% accuracy loss and only 24.1 ns additional delay. These results demonstrate an improved balance between computational speed and resource utilization, making the divider well-suited for high-performance FPGA-based systems with strict resource constraints. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_14611 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | FPGA Design and Implementation of Fixed-Point Fast Divider Using Goldschmidt Division Algorithm and Mitchell Multiplication Algorithm Yang, Jinkun Signal Processing This paper presents a variable bit-width fixed-point fast divider using Goldschmidt division algorithm and Mitchell multiplication algorithm. Described using Verilog HDL and implemented on a Xilinx XC7Z020-2CLG400I FPGA, the proposed divider achieves over 99% computational accuracy with a minimum latency of 99.1 ns, which is 31.7 ns faster than existing single-precision dividers. Compared with a Goldschmidt divider using a Vedic multiplier, the proposed design reduces Slice Registers by 46.68%, Slice LUTs by 4.93%, and Slices by 11.85%, with less than 1% accuracy loss and only 24.1 ns additional delay. These results demonstrate an improved balance between computational speed and resource utilization, making the divider well-suited for high-performance FPGA-based systems with strict resource constraints. |
| title | FPGA Design and Implementation of Fixed-Point Fast Divider Using Goldschmidt Division Algorithm and Mitchell Multiplication Algorithm |
| topic | Signal Processing |
| url | https://arxiv.org/abs/2508.14611 |