Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2508.14899 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866918128194158592 |
|---|---|
| author | Ahmad, Adeel Kamal, Ahmad Tameem Amir, Nouman Zafar, Bilal Nasir, Saad Bin |
| author_facet | Ahmad, Adeel Kamal, Ahmad Tameem Amir, Nouman Zafar, Bilal Nasir, Saad Bin |
| contents | This project enables RISC-V microkernel support in IREE, an MLIR-based machine learning compiler and runtime. The approach begins by enabling the lowering of MLIR linalg dialect contraction ops to linalg.mmt4d op for the RISC-V64 target within the IREE pass pipeline, followed by the development of optimized microkernels for RISC-V. The performance gains are compared with upstream IREE and Llama.cpp for the Llama-3.2-1B-Instruct model. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_14899 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE Ahmad, Adeel Kamal, Ahmad Tameem Amir, Nouman Zafar, Bilal Nasir, Saad Bin Hardware Architecture Artificial Intelligence This project enables RISC-V microkernel support in IREE, an MLIR-based machine learning compiler and runtime. The approach begins by enabling the lowering of MLIR linalg dialect contraction ops to linalg.mmt4d op for the RISC-V64 target within the IREE pass pipeline, followed by the development of optimized microkernels for RISC-V. The performance gains are compared with upstream IREE and Llama.cpp for the Llama-3.2-1B-Instruct model. |
| title | Accelerating GenAI Workloads by Enabling RISC-V Microkernel Support in IREE |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2508.14899 |