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| Auteurs principaux: | , |
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| Format: | Preprint |
| Publié: |
2025
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| Accès en ligne: | https://arxiv.org/abs/2508.15729 |
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| _version_ | 1866908497437786112 |
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| author | Reddy, Harshith Arora, Pankaj |
| author_facet | Reddy, Harshith Arora, Pankaj |
| contents | This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion characteristics, backed by an all-region MOSFET model. The proposed design achieves a very low operating supply voltage of 0.5 V and a remarkably low temperature coefficient of 16.28 ppm/$^\circ$C through the mutual compensation of CTAT, PTAT, and curvature-correction currents, over a wide range from -40 $^\circ$C to 130 $^\circ$C. A stable reference voltage of 205 mV is generated with a line sensitivity of 1.65 %/V and a power supply rejection ratio (PSRR) of -50 dB at 10 kHz. The circuit achieves all these parameters while maintaining a good power efficiency, consuming only 0.67 $μ$W. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_15729 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | A 16.28 ppm/$^\circ$C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference with Curvature Compensation Reddy, Harshith Arora, Pankaj Systems and Control This paper presents a fully-integrated CMOS voltage reference designed in a 90 nm process node using low voltage threshold (LVT) transistor models. The voltage reference leverages subthreshold operation and near-weak inversion characteristics, backed by an all-region MOSFET model. The proposed design achieves a very low operating supply voltage of 0.5 V and a remarkably low temperature coefficient of 16.28 ppm/$^\circ$C through the mutual compensation of CTAT, PTAT, and curvature-correction currents, over a wide range from -40 $^\circ$C to 130 $^\circ$C. A stable reference voltage of 205 mV is generated with a line sensitivity of 1.65 %/V and a power supply rejection ratio (PSRR) of -50 dB at 10 kHz. The circuit achieves all these parameters while maintaining a good power efficiency, consuming only 0.67 $μ$W. |
| title | A 16.28 ppm/$^\circ$C Temperature Coefficient, 0.5V Low-Voltage CMOS Voltage Reference with Curvature Compensation |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2508.15729 |