Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
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arXiv
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| Hauptverfasser: | , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866917087833751552 |
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| author | Kumar, Vineet M, Ajay Kumar Li, Yike Shanker, Shreejith John, Deepu |
| author_facet | Kumar, Vineet M, Ajay Kumar Li, Yike Shanker, Shreejith John, Deepu |
| contents | This paper presents a novel System-on-Chip (SoC) architecture for accelerating complex deep learning models for edge computing applications through a combination of hardware and software optimisations. The hardware architecture tightly couples the open-source NVIDIA Deep Learning Accelerator (NVDLA) to a 32-bit, 4-stage pipelined RISC-V core from Codasip called uRISC_V. To offload the model acceleration in software, our toolflow generates bare-metal application code (in assembly), overcoming complex OS overheads of previous works that have explored similar architectures. This tightly coupled architecture and bare-metal flow leads to improvements in execution speed and storage efficiency, making it suitable for edge computing solutions. We evaluate the architecture on AMD's ZCU102 FPGA board using NVDLA-small configuration and test the flow using LeNet-5, ResNet-18 and ResNet-50 models. Our results show that these models can perform inference in 4.8 ms, 16.2 ms and 1.1 s respectively, at a system clock frequency of 100 MHz. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_16095 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference Kumar, Vineet M, Ajay Kumar Li, Yike Shanker, Shreejith John, Deepu Hardware Architecture This paper presents a novel System-on-Chip (SoC) architecture for accelerating complex deep learning models for edge computing applications through a combination of hardware and software optimisations. The hardware architecture tightly couples the open-source NVIDIA Deep Learning Accelerator (NVDLA) to a 32-bit, 4-stage pipelined RISC-V core from Codasip called uRISC_V. To offload the model acceleration in software, our toolflow generates bare-metal application code (in assembly), overcoming complex OS overheads of previous works that have explored similar architectures. This tightly coupled architecture and bare-metal flow leads to improvements in execution speed and storage efficiency, making it suitable for edge computing solutions. We evaluate the architecture on AMD's ZCU102 FPGA board using NVDLA-small configuration and test the flow using LeNet-5, ResNet-18 and ResNet-50 models. Our results show that these models can perform inference in 4.8 ms, 16.2 ms and 1.1 s respectively, at a system clock frequency of 100 MHz. |
| title | Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.16095 |