Bare-Metal RISC-V + NVDLA SoC for Efficient Deep Learning Inference
Fuente:
arXiv
Saved in:
| Main Authors: | Kumar, Vineet, M, Ajay Kumar, Li, Yike, Shanker, Shreejith, John, Deepu |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
by: M, Ajay Kumar, et al.
Published: (2025)
by: M, Ajay Kumar, et al.
Published: (2025)
NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16
by: Schmulbach, Viansa, et al.
Published: (2025)
by: Schmulbach, Viansa, et al.
Published: (2025)
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
by: Al-Qawlaq, Aness, et al.
Published: (2024)
by: Al-Qawlaq, Aness, et al.
Published: (2024)
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)
by: Valente, Luca, et al.
Published: (2022)
Chiplet-Based RISC-V SoC with Modular AI Acceleration
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)
LogicSparse: Enabling Engine-Free Unstructured Sparsity for Quantised Deep-learning Accelerators
by: Li, Changhong, et al.
Published: (2025)
by: Li, Changhong, et al.
Published: (2025)
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality with At-MRAM Neural Engine
by: Prasad, Arpan Suravi, et al.
Published: (2023)
by: Prasad, Arpan Suravi, et al.
Published: (2023)
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)
by: Scheffler, Paul, et al.
Published: (2024)
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs
by: Koenig, Cyril, et al.
Published: (2025)
by: Koenig, Cyril, et al.
Published: (2025)
Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
by: Vanoni, Axel, et al.
Published: (2026)
by: Vanoni, Axel, et al.
Published: (2026)
A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation
by: Valente, Luca, et al.
Published: (2024)
by: Valente, Luca, et al.
Published: (2024)
A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems
by: Bonet, Marc Solé i, et al.
Published: (2025)
by: Bonet, Marc Solé i, et al.
Published: (2025)
Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
by: Sauter, Phillippe, et al.
Published: (2024)
by: Sauter, Phillippe, et al.
Published: (2024)
Fused-Tiled Layers: Minimizing Data Movement on RISC-V SoCs with Software-Managed Caches
by: Jung, Victor J. B., et al.
Published: (2025)
by: Jung, Victor J. B., et al.
Published: (2025)
An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
by: Sekonji, Mohammad Javad, et al.
Published: (2026)
by: Sekonji, Mohammad Javad, et al.
Published: (2026)
FeNN-DMA: A RISC-V SoC for SNN acceleration
by: Aizaz, Zainab, et al.
Published: (2025)
by: Aizaz, Zainab, et al.
Published: (2025)
Tensor Manipulation Unit (TMU): Reconfigurable, Near-Memory Tensor Manipulation for High-Throughput AI SoC
by: Zhou, Weiyu, et al.
Published: (2025)
by: Zhou, Weiyu, et al.
Published: (2025)
An Energy-Efficient Artefact Detection Accelerator on FPGAs for Hyper-Spectral Satellite Imagery
by: Castelino, Cornell, et al.
Published: (2024)
by: Castelino, Cornell, et al.
Published: (2024)
System-Level Isolation for Mixed-Criticality RISC-V SoCs: A "World" Reality Check
by: Cunha, Luis, et al.
Published: (2026)
by: Cunha, Luis, et al.
Published: (2026)
SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
by: Gunawardana, Kanishka, et al.
Published: (2026)
by: Gunawardana, Kanishka, et al.
Published: (2026)
FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security Strategies
by: Li, Changhong, et al.
Published: (2025)
by: Li, Changhong, et al.
Published: (2025)
Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS
by: Sauter, Philippe, et al.
Published: (2025)
by: Sauter, Philippe, et al.
Published: (2025)
SecCAN: An Extended CAN Controller with Embedded Intrusion Detection
by: Khandelwal, Shashwat, et al.
Published: (2025)
by: Khandelwal, Shashwat, et al.
Published: (2025)
Simopt-Power: Leveraging Simulation Metadata for Low-Power Design Synthesis
by: Wadhwa, Eashan, et al.
Published: (2025)
by: Wadhwa, Eashan, et al.
Published: (2025)
Teardown Analysis of Samsung S20 Exynos 990 SoC
by: Jadoon, Nabeel Ahmad Khan, et al.
Published: (2025)
by: Jadoon, Nabeel Ahmad Khan, et al.
Published: (2025)
Simopt -- Simulation pass for Speculative Optimisation of FPGA-CAD flow
by: Wadhwa, Eashan, et al.
Published: (2024)
by: Wadhwa, Eashan, et al.
Published: (2024)
A High-Efficiency SoC for Next-Generation Mobile DNA Sequencing
by: Beyene, Abel, et al.
Published: (2025)
by: Beyene, Abel, et al.
Published: (2025)
TOP: Towards Open & Predictable Heterogeneous SoCs
by: Valente, Luca, et al.
Published: (2024)
by: Valente, Luca, et al.
Published: (2024)
Exploring Highly Quantised Neural Networks for Intrusion Detection in Automotive CAN
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN
by: Khandelwal, Shashwat, et al.
Published: (2024)
by: Khandelwal, Shashwat, et al.
Published: (2024)
Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space
by: Leon, Vasileios, et al.
Published: (2025)
by: Leon, Vasileios, et al.
Published: (2025)
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
by: Rogenmoser, Michael, et al.
Published: (2024)
by: Rogenmoser, Michael, et al.
Published: (2024)
Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designs
by: Wadhwa, Eashan, et al.
Published: (2026)
by: Wadhwa, Eashan, et al.
Published: (2026)
From Circuits to SoC Processors: Arithmetic Approximation Techniques & Embedded Computing Methodologies for DSP Acceleration
by: Leon, Vasileios
Published: (2023)
by: Leon, Vasileios
Published: (2023)
Development of High-Performance DSP Algorithms on the European Rad-Hard NG-ULTRA SoC FPGA
by: Leon, Vasileios, et al.
Published: (2024)
by: Leon, Vasileios, et al.
Published: (2024)
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm
by: Liu, Meng, et al.
Published: (2024)
by: Liu, Meng, et al.
Published: (2024)
Non-interfering On-line and In-field SoC Testing
by: Strauch, Tobias
Published: (2024)
by: Strauch, Tobias
Published: (2024)
A Scalable RISC-V Vector Processor Enabling Efficient Multi-Precision DNN Inference
by: Wang, Chuanning, et al.
Published: (2024)
by: Wang, Chuanning, et al.
Published: (2024)
Sequencing on Silicon: AI SoC Design for Mobile Genomics at the Edge
by: Magierowski, Sebastian, et al.
Published: (2025)
by: Magierowski, Sebastian, et al.
Published: (2025)
PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC
by: Ribeiro, Lucas Grativol, et al.
Published: (2024)
by: Ribeiro, Lucas Grativol, et al.
Published: (2024)
Similar Items
-
MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
by: M, Ajay Kumar, et al.
Published: (2025) -
NeCTAr: A Heterogeneous RISC-V SoC for Language Model Inference in Intel 16
by: Schmulbach, Viansa, et al.
Published: (2025) -
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
by: Al-Qawlaq, Aness, et al.
Published: (2024) -
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022) -
Chiplet-Based RISC-V SoC with Modular AI Acceleration
by: Bharadwaj, Suhas Suresh, et al.
Published: (2025)