ARSP: Automated Repair of Verilog Designs via Semantic Partitioning
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866909749326381056 |
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| author | Yao, Bingkun Wang, Ning Liu, Xiangfeng Du, Yuxin Hu, Yuchen Gao, Hong Jiang, Zhe Guan, Nan |
| author_facet | Yao, Bingkun Wang, Ning Liu, Xiangfeng Du, Yuxin Hu, Yuchen Gao, Hong Jiang, Zhe Guan, Nan |
| contents | Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this effort, existing LLM-based automated debugging methods underperform on industrial-scale modules. A major reason for this is bug signal dilution in long contexts, where a few bug-relevant tokens are overwhelmed by hundreds of unrelated lines, diffusing the model's attention. To address this issue, we introduce ARSP, a two-stage system that mitigates dilution via semantics-guided fragmentation. A Partition LLM splits a module into semantically tight fragments; a Repair LLM patches each fragment; edits are merged without altering unrelated logic. A synthetic data framework generates fragment-level training pairs spanning bug types, design styles, and scales to supervise both models. Experiments show that ARSP achieves 77.92% pass@1 and 83.88% pass@5, outperforming mainstream commercial LLMs including Claude-3.7 and SOTA automated Verilog debugging tools Strider and MEIC. Also, semantic partitioning improves pass@1 by 11.6% and pass@5 by 10.2% over whole-module debugging, validating the effectiveness of fragment-level scope reduction in LLM-based Verilog debugging. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_16517 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | ARSP: Automated Repair of Verilog Designs via Semantic Partitioning Yao, Bingkun Wang, Ning Liu, Xiangfeng Du, Yuxin Hu, Yuchen Gao, Hong Jiang, Zhe Guan, Nan Software Engineering Programming Languages Debugging functional Verilog bugs consumes a significant portion of front-end design time. While Large Language Models (LLMs) have demonstrated great potential in mitigating this effort, existing LLM-based automated debugging methods underperform on industrial-scale modules. A major reason for this is bug signal dilution in long contexts, where a few bug-relevant tokens are overwhelmed by hundreds of unrelated lines, diffusing the model's attention. To address this issue, we introduce ARSP, a two-stage system that mitigates dilution via semantics-guided fragmentation. A Partition LLM splits a module into semantically tight fragments; a Repair LLM patches each fragment; edits are merged without altering unrelated logic. A synthetic data framework generates fragment-level training pairs spanning bug types, design styles, and scales to supervise both models. Experiments show that ARSP achieves 77.92% pass@1 and 83.88% pass@5, outperforming mainstream commercial LLMs including Claude-3.7 and SOTA automated Verilog debugging tools Strider and MEIC. Also, semantic partitioning improves pass@1 by 11.6% and pass@5 by 10.2% over whole-module debugging, validating the effectiveness of fragment-level scope reduction in LLM-based Verilog debugging. |
| title | ARSP: Automated Repair of Verilog Designs via Semantic Partitioning |
| topic | Software Engineering Programming Languages |
| url | https://arxiv.org/abs/2508.16517 |