Targeted Wearout Attacks in Microprocessor Cores
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866912551263010816 |
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| author | Mashburn, Joshua Knechtel, Johann Klemme, Florian Amrouch, Hussam Sinanoglu, Ozgur Gratz, Paul V. |
| author_facet | Mashburn, Joshua Knechtel, Johann Klemme, Florian Amrouch, Hussam Sinanoglu, Ozgur Gratz, Paul V. |
| contents | Negative-Bias Temperature Instability is a dominant aging mechanism in nanoscale CMOS circuits such as microprocessors. With this aging mechanism, the rate of device aging is dependent not only on overall operating conditions, such as heat, but also on user controllable inputs to the transistors. This dependence on input implies a possible timing fault-injection attack wherein a targeted path of logic is intentionally degraded through the purposeful, software-driven actions of an attacker, rendering a targeted bit effectively stuck.
In this work, we describe such an attack mechanism, which we dub a "$\textbf{Targeted Wearout Attack}$", wherein an attacker with sufficient knowledge of the processor core, executing a carefully crafted software program with only user privilege, is able to degrade a functional unit within the processor with the aim of eliciting a particular desired incorrect calculation in a victim application. Here we give a general methodology for the attack. We then demonstrate a case study where a targeted path within the fused multiply-add pipeline in a RISC-V CPU sees a $>7x$ increase in wear over time than would be experienced under typical workloads. We show that an attacker could leverage such an attack, leading to targeted and silent data corruption in a co-running victim application using the same unit. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_16868 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Targeted Wearout Attacks in Microprocessor Cores Mashburn, Joshua Knechtel, Johann Klemme, Florian Amrouch, Hussam Sinanoglu, Ozgur Gratz, Paul V. Cryptography and Security Hardware Architecture Negative-Bias Temperature Instability is a dominant aging mechanism in nanoscale CMOS circuits such as microprocessors. With this aging mechanism, the rate of device aging is dependent not only on overall operating conditions, such as heat, but also on user controllable inputs to the transistors. This dependence on input implies a possible timing fault-injection attack wherein a targeted path of logic is intentionally degraded through the purposeful, software-driven actions of an attacker, rendering a targeted bit effectively stuck. In this work, we describe such an attack mechanism, which we dub a "$\textbf{Targeted Wearout Attack}$", wherein an attacker with sufficient knowledge of the processor core, executing a carefully crafted software program with only user privilege, is able to degrade a functional unit within the processor with the aim of eliciting a particular desired incorrect calculation in a victim application. Here we give a general methodology for the attack. We then demonstrate a case study where a targeted path within the fused multiply-add pipeline in a RISC-V CPU sees a $>7x$ increase in wear over time than would be experienced under typical workloads. We show that an attacker could leverage such an attack, leading to targeted and silent data corruption in a co-running victim application using the same unit. |
| title | Targeted Wearout Attacks in Microprocessor Cores |
| topic | Cryptography and Security Hardware Architecture |
| url | https://arxiv.org/abs/2508.16868 |