TSPC-PFD: TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector
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| Main Authors: | , , , |
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| Format: | Preprint |
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2025
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| _version_ | 1866916913617043456 |
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| author | Challagundla, Dhandeep Sundarapu, Venkata Krishna Vamsi Bezzam, Ignatius Islam, Riadul |
| author_facet | Challagundla, Dhandeep Sundarapu, Venkata Krishna Vamsi Bezzam, Ignatius Islam, Riadul |
| contents | Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of 4.41 uW at 3 GHz input frequency with a layout area of $10.42μm^2$. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_16933 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | TSPC-PFD: TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector Challagundla, Dhandeep Sundarapu, Venkata Krishna Vamsi Bezzam, Ignatius Islam, Riadul Emerging Technologies Signal Processing Phase Frequency Detectors (PFDs) are essential components in Phase-Locked Loop (PLL) and Delay-Locked Loop (DLL) systems, responsible for comparing phase and frequency differences and generating up/down signals to regulate charge pumps and/or, consequently, Voltage-Controlled Oscillators (VCOs). Conventional PFD designs often suffer from significant dead zones and blind zones, which degrade phase detection accuracy and increase jitter in high-speed applications. This paper addresses PFD design challenges and presents a novel low-power True Single-Phase Clock (TSPC)-based PFD. The proposed design eliminates the blind zone entirely while achieving a minimal dead zone of 40 ps. The proposed PFD, implemented using TSMC 28 nm technology, demonstrates a low-power consumption of 4.41 uW at 3 GHz input frequency with a layout area of $10.42μm^2$. |
| title | TSPC-PFD: TSPC-Based Low-Power High-Resolution CMOS Phase Frequency Detector |
| topic | Emerging Technologies Signal Processing |
| url | https://arxiv.org/abs/2508.16933 |