X-HEEP: An Open-Source, Configurable and Extendible RISC-V Platform for TinyAI Applications
Fuente:
arXiv
Saved in:
| Main Authors: | Machetti, Simone, Schiavone, Pasquale Davide, Ansaloni, Giovanni, Peón-Quirós, Miguel, Atienza, David |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators
by: Machetti, Simone, et al.
Published: (2024)
by: Machetti, Simone, et al.
Published: (2024)
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025)
by: Machetti, Simone, et al.
Published: (2025)
Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems
by: Machetti, Simone, et al.
Published: (2025)
by: Machetti, Simone, et al.
Published: (2025)
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
by: Caon, Michele, et al.
Published: (2024)
by: Caon, Michele, et al.
Published: (2024)
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
by: Cammarata, Danilo, et al.
Published: (2025)
by: Cammarata, Danilo, et al.
Published: (2025)
ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
by: Petrolo, Vincenzo, et al.
Published: (2025)
by: Petrolo, Vincenzo, et al.
Published: (2025)
MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots
by: Amirshahi, Alireza, et al.
Published: (2024)
by: Amirshahi, Alireza, et al.
Published: (2024)
Not All Faults Are Equal: Transient-Fault Sensitivity Characterization of an Open-Source RISC-V Vector Cluster
by: Cai, Maoyuan, et al.
Published: (2026)
by: Cai, Maoyuan, et al.
Published: (2026)
Increasing the Energy-Efficiency of Wearables Using Low-Precision Posit Arithmetic with PHEE
by: Mallasén, David, et al.
Published: (2025)
by: Mallasén, David, et al.
Published: (2025)
MEDEA: A Design-Time Multi-Objective Manager for Energy-Efficient DNN Inference on Heterogeneous Ultra-Low Power Platforms
by: Taji, Hossein, et al.
Published: (2025)
by: Taji, Hossein, et al.
Published: (2025)
Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA
by: Carpentieri, Nicolò, et al.
Published: (2024)
by: Carpentieri, Nicolò, et al.
Published: (2024)
Work-In-Progress: Accelerating Numpy With OpenBLAS For Open-Source RISC-V Chips
by: Koenig, Cyril, et al.
Published: (2025)
by: Koenig, Cyril, et al.
Published: (2025)
Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
by: Fu, Zexin, et al.
Published: (2025)
by: Fu, Zexin, et al.
Published: (2025)
Exploiting pre-optimized kernels with polyhedral transformations for CGRA compilation
by: Wang, Yuxuan, et al.
Published: (2026)
by: Wang, Yuxuan, et al.
Published: (2026)
A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
by: Delavari, Arvin, et al.
Published: (2024)
by: Delavari, Arvin, et al.
Published: (2024)
Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon
by: Sauter, Phillippe, et al.
Published: (2025)
by: Sauter, Phillippe, et al.
Published: (2025)
Just TestIt! An SBST Approach To Automate System-Integration Testing
by: Terzano, Tommaso, et al.
Published: (2025)
by: Terzano, Tommaso, et al.
Published: (2025)
Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
by: McDougall, Ian, et al.
Published: (2025)
by: McDougall, Ian, et al.
Published: (2025)
Physical Design of UET-RVMCU: A Streamlined Open-Source RISC-V Microcontroller
by: Azhar, Abdullah, et al.
Published: (2026)
by: Azhar, Abdullah, et al.
Published: (2026)
Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
by: Vanoni, Axel, et al.
Published: (2026)
by: Vanoni, Axel, et al.
Published: (2026)
Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
by: Sauter, Phillippe, et al.
Published: (2024)
by: Sauter, Phillippe, et al.
Published: (2024)
STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems
by: Vazquez, Daniel, et al.
Published: (2024)
by: Vazquez, Daniel, et al.
Published: (2024)
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)
by: Scheffler, Paul, et al.
Published: (2024)
Functional ISS-Driven Verification of Superscalar RISC-V Processors
by: Galimberti, Andrea, et al.
Published: (2024)
by: Galimberti, Andrea, et al.
Published: (2024)
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
by: Perotti, Matteo, et al.
Published: (2022)
by: Perotti, Matteo, et al.
Published: (2022)
HyperCroc: End-to-End Open-Source RISC-V MCU with a Plug-In Interface for Domain-Specific Accelerators
by: Sauter, Philippe, et al.
Published: (2026)
by: Sauter, Philippe, et al.
Published: (2026)
Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6
by: Laghi, Umberto, et al.
Published: (2025)
by: Laghi, Umberto, et al.
Published: (2025)
GeneTEK: Low-power, high-performance and scalable FPGA architecture for exact unit-cost edit distance
by: Espinosa, Elena, et al.
Published: (2025)
by: Espinosa, Elena, et al.
Published: (2025)
KWT-Tiny: RISC-V Accelerated, Embedded Keyword Spotting Transformer
by: Al-Qawlaq, Aness, et al.
Published: (2024)
by: Al-Qawlaq, Aness, et al.
Published: (2024)
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
by: Perotti, Matteo, et al.
Published: (2024)
by: Perotti, Matteo, et al.
Published: (2024)
SAT-based Exact Modulo Scheduling Mapping for Resource-Constrained CGRAs
by: Tirelli, Cristian, et al.
Published: (2024)
by: Tirelli, Cristian, et al.
Published: (2024)
REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton
by: Oliete-Escuín, Noelia, et al.
Published: (2026)
by: Oliete-Escuín, Noelia, et al.
Published: (2026)
HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC
by: Valente, Luca, et al.
Published: (2022)
by: Valente, Luca, et al.
Published: (2022)
WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
by: Giorgi, Roberto, et al.
Published: (2025)
by: Giorgi, Roberto, et al.
Published: (2025)
Wildcat: Educational RISC-V Microprocessors
by: Schoeberl, Martin
Published: (2025)
by: Schoeberl, Martin
Published: (2025)
CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device
by: and, Yan-Cheng Guo, et al.
Published: (2025)
by: and, Yan-Cheng Guo, et al.
Published: (2025)
NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip
by: Silva, Anderson I., et al.
Published: (2024)
by: Silva, Anderson I., et al.
Published: (2024)
CVA6-CFI: A First Glance at RISC-V Control-Flow Integrity Extensions
by: Manoni, Simone, et al.
Published: (2026)
by: Manoni, Simone, et al.
Published: (2026)
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation
by: Ottaviano, Alessandro, et al.
Published: (2023)
by: Ottaviano, Alessandro, et al.
Published: (2023)
Hypervisor Extension for a RISC-V Processor
by: Gauchola, Jaume, et al.
Published: (2024)
by: Gauchola, Jaume, et al.
Published: (2024)
Similar Items
-
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators
by: Machetti, Simone, et al.
Published: (2024) -
e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications
by: Machetti, Simone, et al.
Published: (2025) -
Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems
by: Machetti, Simone, et al.
Published: (2025) -
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
by: Caon, Michele, et al.
Published: (2024) -
Quadrilatero: A RISC-V programmable matrix coprocessor for low-power edge applications
by: Cammarata, Danilo, et al.
Published: (2025)