Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA Acceleration
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arXiv
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| Main Authors: | Yin, Mengyuan, Choong, Benjamin Chen Ming, Qu, Chuping, Goh, Rick Siow Mong, Wong, Weng-Fai, Luo, Tao |
|---|---|
| Format: | Preprint |
| Published: |
2025
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| Subjects: | |
| Online Access: | |
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