Saved in:
| Main Authors: | Sahruri, Abdullah, Margala, Martin |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2508.17809 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption
by: Yune, Sungwoong, et al.
Published: (2025)
by: Yune, Sungwoong, et al.
Published: (2025)
Do Not Trust Power Management: A Survey on Internal Energy-based Attacks Circumventing Trusted Execution Environments Security Properties
by: Gonidec, Gwenn Le, et al.
Published: (2024)
by: Gonidec, Gwenn Le, et al.
Published: (2024)
SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
by: Razmkhah, Sasan, et al.
Published: (2025)
by: Razmkhah, Sasan, et al.
Published: (2025)
In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
by: Ovy, Sanwar Ahmed, et al.
Published: (2025)
by: Ovy, Sanwar Ahmed, et al.
Published: (2025)
Research Directions for Verifiable Crypto-Physically Secure TEEs
by: Bellemare, Sylvain
Published: (2024)
by: Bellemare, Sylvain
Published: (2024)
Control-Flow Attestation: Concepts, Solutions, and Open Challenges
by: Sha, Zhanyu, et al.
Published: (2024)
by: Sha, Zhanyu, et al.
Published: (2024)
Memristor-Based Lightweight Encryption
by: Siddiqi, Muhammad Ali, et al.
Published: (2024)
by: Siddiqi, Muhammad Ali, et al.
Published: (2024)
DARTH-PUM: A Hybrid Processing-Using-Memory Architecture
by: Wong, Ryan, et al.
Published: (2026)
by: Wong, Ryan, et al.
Published: (2026)
The Impact of Logic Locking on Confidentiality: An Automated Evaluation
by: Reimann, Lennart M., et al.
Published: (2025)
by: Reimann, Lennart M., et al.
Published: (2025)
Utilizing Layout Effects for Analog Logic Locking
by: Aljafar, Muayad J., et al.
Published: (2024)
by: Aljafar, Muayad J., et al.
Published: (2024)
Integrated Security Mechanisms for Weight Protection in Memristive Crossbar Arrays
by: Rahman, Muhammad Faheemur, et al.
Published: (2025)
by: Rahman, Muhammad Faheemur, et al.
Published: (2025)
Single-Cell Universal Logic-in-Memory Using 2T-nC FeRAM: An Area and Energy-Efficient Approach for Bulk Bitwise Computation
by: Biswas, Rudra, et al.
Published: (2025)
by: Biswas, Rudra, et al.
Published: (2025)
Scaling up Reversible Logic with HKI Superconducting Inductors
by: DeBenedictis, Erik P.
Published: (2025)
by: DeBenedictis, Erik P.
Published: (2025)
Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction
by: Reimann, Lennart M., et al.
Published: (2024)
by: Reimann, Lennart M., et al.
Published: (2024)
A Novel 8T SRAM-Based In-Memory Computing Architecture for MAC-Derived Logical Functions
by: M, Amogh K, et al.
Published: (2025)
by: M, Amogh K, et al.
Published: (2025)
Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits
by: Zhang, Xiameng, et al.
Published: (2026)
by: Zhang, Xiameng, et al.
Published: (2026)
Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock
by: Choi, Suhyeong, et al.
Published: (2024)
by: Choi, Suhyeong, et al.
Published: (2024)
TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
by: Liu, Yuntao, et al.
Published: (2023)
by: Liu, Yuntao, et al.
Published: (2023)
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring
by: Tsaras, Dimitris, et al.
Published: (2025)
by: Tsaras, Dimitris, et al.
Published: (2025)
Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)
by: Karn, Rupesh Raj, et al.
Published: (2025)
Reimagining Voltage-Controlled Cryogenic Boolean Logic Paradigm with Quantum-Enhanced Josephson Junction FETs
by: Islam, Md Mazharul, et al.
Published: (2025)
by: Islam, Md Mazharul, et al.
Published: (2025)
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)
by: Wang, Fangzhou, et al.
Published: (2024)
PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro with In-Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout
by: Chen, Zhiyu, et al.
Published: (2024)
by: Chen, Zhiyu, et al.
Published: (2024)
Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures
by: Razi, Farzad, et al.
Published: (2026)
by: Razi, Farzad, et al.
Published: (2026)
On the Influence of the Laser Illumination on the Logic Cells Current Consumption
by: Petryk, Dmytro, et al.
Published: (2024)
by: Petryk, Dmytro, et al.
Published: (2024)
HiSEP-Q: A Highly Scalable and Efficient Quantum Control Processor for Superconducting Qubits
by: Guo, Xiaorang, et al.
Published: (2023)
by: Guo, Xiaorang, et al.
Published: (2023)
Function Approximation Using Analog Building Blocks in Flexible Electronics
by: Duarte, Paula Carolina Lozano, et al.
Published: (2025)
by: Duarte, Paula Carolina Lozano, et al.
Published: (2025)
Length-Matching Routing for Programmable Photonic Circuits Using Best-First Strategy
by: Wang, Xiaoke, et al.
Published: (2025)
by: Wang, Xiaoke, et al.
Published: (2025)
Analog-to-Stochastic Converter Using Magnetic Tunnel Junction Devices for Vision Chips
by: Onizawa, Naoya, et al.
Published: (2026)
by: Onizawa, Naoya, et al.
Published: (2026)
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
by: Sheikh, Ahmad T., et al.
Published: (2024)
by: Sheikh, Ahmad T., et al.
Published: (2024)
Robust and Attack Resilient Logic Locking with a High Application-Level Impact
by: Liu, Yuntao, et al.
Published: (2021)
by: Liu, Yuntao, et al.
Published: (2021)
Learning-driven Physically-aware Large-scale Circuit Gate Sizing
by: Ye, Yuyang, et al.
Published: (2024)
by: Ye, Yuyang, et al.
Published: (2024)
Enabling Efficient and Scalable DRAM Read Disturbance Mitigation via New Experimental Insights into Modern DRAM Chips
by: Yağlıkçı, Abdullah Giray
Published: (2024)
by: Yağlıkçı, Abdullah Giray
Published: (2024)
A wave-geometric duality for hyperdimensional computing
by: Poore, Tyler L.
Published: (2026)
by: Poore, Tyler L.
Published: (2026)
A Low-Cost Reliable Racetrack Cache Based on Data Compression
by: Cheshmikhani, Elham, et al.
Published: (2025)
by: Cheshmikhani, Elham, et al.
Published: (2025)
$R^4$: A Racetrack Register File with Runtime Software Reconfiguration
by: Hakert, Christian, et al.
Published: (2025)
by: Hakert, Christian, et al.
Published: (2025)
Towards Memory Specialization: A Case for Long-Term and Short-Term RAM
by: Li, Peijing, et al.
Published: (2025)
by: Li, Peijing, et al.
Published: (2025)
Cognition Engines: A Row-Scale HVDC Architecture for Computational Continuity of AI
by: Churnock, Paul
Published: (2025)
by: Churnock, Paul
Published: (2025)
A Novel Low-Power Cache Architecture Based on 6-Transistor SRAM Cells
by: Dizabadi, Naser Khatti, et al.
Published: (2026)
by: Dizabadi, Naser Khatti, et al.
Published: (2026)
ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks
by: Sedaghatgoo, Ali, et al.
Published: (2024)
by: Sedaghatgoo, Ali, et al.
Published: (2024)
Similar Items
-
ABC-FHE : A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic Encryption
by: Yune, Sungwoong, et al.
Published: (2025) -
Do Not Trust Power Management: A Survey on Internal Energy-based Attacks Circumventing Trusted Execution Environments Security Properties
by: Gonidec, Gwenn Le, et al.
Published: (2024) -
SCE-NTT: A Hardware Accelerator for Number Theoretic Transform Using Superconductor Electronics
by: Razmkhah, Sasan, et al.
Published: (2025) -
In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
by: Ovy, Sanwar Ahmed, et al.
Published: (2025) -
Research Directions for Verifiable Crypto-Physically Secure TEEs
by: Bellemare, Sylvain
Published: (2024)