SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study
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| Natura: | Preprint |
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2025
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| author | Xiang, Yang García-Redondo, Fernando Sharma, Arvind Nguyen, Van Dai Fantini, Andrea Matagne, Philippe Rao, Siddharth Subhechha, Subhali Verschueren, Lynn Baig, Mohammed Aftab Bardon, Marie Garcia Hellings, Geert |
| author_facet | Xiang, Yang García-Redondo, Fernando Sharma, Arvind Nguyen, Van Dai Fantini, Andrea Matagne, Philippe Rao, Siddharth Subhechha, Subhali Verschueren, Lynn Baig, Mohammed Aftab Bardon, Marie Garcia Hellings, Geert |
| contents | This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10 -- 40) % bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1 -- 100) s retention targets. This is particularly to attribute to their (i) more available Si fins for write transistor and (ii) lower bitline resistance at reduced cell width. We nevertheless underscore the read tradeoff associated with BEOL RSs, with the low-drive IGZO-FET selector sacrificing the latency up to (3 -- 5) ns and the imperfectly rectifying diode selectors suffering (2.5 -- 5)$\times$ energy cost relative to 2T1R. This article thus highlights the realistic prospects and hurdles of BEOL RSs towards holistic power-performance-area scaling of SOT-MRAM. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_18250 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study Xiang, Yang García-Redondo, Fernando Sharma, Arvind Nguyen, Van Dai Fantini, Andrea Matagne, Philippe Rao, Siddharth Subhechha, Subhali Verschueren, Lynn Baig, Mohammed Aftab Bardon, Marie Garcia Hellings, Geert Emerging Technologies This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive Design-Technology Co-Optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10 -- 40) % bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1 -- 100) s retention targets. This is particularly to attribute to their (i) more available Si fins for write transistor and (ii) lower bitline resistance at reduced cell width. We nevertheless underscore the read tradeoff associated with BEOL RSs, with the low-drive IGZO-FET selector sacrificing the latency up to (3 -- 5) ns and the imperfectly rectifying diode selectors suffering (2.5 -- 5)$\times$ energy cost relative to 2T1R. This article thus highlights the realistic prospects and hurdles of BEOL RSs towards holistic power-performance-area scaling of SOT-MRAM. |
| title | SOT-MRAM Bitcell Scaling with BEOL Read Selectors: A DTCO Study |
| topic | Emerging Technologies |
| url | https://arxiv.org/abs/2508.18250 |