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VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning

Fuente: arXiv

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Detalles Bibliográficos
Autores principales:	Teng, Fu, Pan, Miao, Zhang, Xuhong, He, Zhezhi, Yang, Yiyao, Chai, Xinyi, Qi, Mengnan, Lu, Liqiang, Yin, Jianwei
Formato:	Preprint
Publicado:	2025
Materias:	Machine Learning Artificial Intelligence
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

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