SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866915463769882624 |
|---|---|
| author | Xuan, Wei Wang, Zhongrui Feng, Lang Lin, Ning Xuan, Zihao Fu, Rongliang Ho, Tsung-Yi Jiao, Yuzhong Liang, Luhong |
| author_facet | Xuan, Wei Wang, Zhongrui Feng, Lang Lin, Ning Xuan, Zihao Fu, Rongliang Ho, Tsung-Yi Jiao, Yuzhong Liang, Luhong |
| contents | Ensuring the confidentiality and integrity of DNN accelerators is paramount across various scenarios spanning autonomous driving, healthcare, and finance. However, current security approaches typically require extensive hardware resources, and incur significant off-chip memory access overheads. This paper introduces SeDA, which utilizes 1) a bandwidth-aware encryption mechanism to improve hardware resource efficiency, 2) optimal block granularity through intra-layer and inter-layer tiling patterns, and 3) a multi-level integrity verification mechanism that minimizes, or even eliminates, memory access overheads. Experimental results show that SeDA decreases performance overhead by over 12% for both server and edge neural processing units (NPUs), while ensuring robust scalability. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_18924 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy Xuan, Wei Wang, Zhongrui Feng, Lang Lin, Ning Xuan, Zihao Fu, Rongliang Ho, Tsung-Yi Jiao, Yuzhong Liang, Luhong Hardware Architecture Ensuring the confidentiality and integrity of DNN accelerators is paramount across various scenarios spanning autonomous driving, healthcare, and finance. However, current security approaches typically require extensive hardware resources, and incur significant off-chip memory access overheads. This paper introduces SeDA, which utilizes 1) a bandwidth-aware encryption mechanism to improve hardware resource efficiency, 2) optimal block granularity through intra-layer and inter-layer tiling patterns, and 3) a multi-level integrity verification mechanism that minimizes, or even eliminates, memory access overheads. Experimental results show that SeDA decreases performance overhead by over 12% for both server and edge neural processing units (NPUs), while ensuring robust scalability. |
| title | SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.18924 |