OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
Fuente:
arXiv
Saved in:
| Main Authors: | Sarkar, Rishov, Hao, Cong |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization
by: Sarkar, Rishov, et al.
Published: (2024)
by: Sarkar, Rishov, et al.
Published: (2024)
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025)
by: Abi-Karam, Stefan, et al.
Published: (2025)
Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim
by: Ali, Wajid, et al.
Published: (2025)
by: Ali, Wajid, et al.
Published: (2025)
SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs
by: Dang, Jingtian, et al.
Published: (2026)
by: Dang, Jingtian, et al.
Published: (2026)
ACALSim: A Scalable Parallel Simulation Framework for High-Performance System Design Space Exploration
by: Lin, Wei-Fen, et al.
Published: (2026)
by: Lin, Wei-Fen, et al.
Published: (2026)
OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs
by: Seyedfaraji, Saeed, et al.
Published: (2024)
by: Seyedfaraji, Saeed, et al.
Published: (2024)
Accelerating Transistor-Level Simulation of Integrated Circuits via Equivalence of RC Long-Chain Structures
by: Tang, Ruibai, et al.
Published: (2025)
by: Tang, Ruibai, et al.
Published: (2025)
Data-Driven Power Modeling and Monitoring via Hardware Performance Counter Tracking
by: Mazzola, Sergio, et al.
Published: (2025)
by: Mazzola, Sergio, et al.
Published: (2025)
SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis
by: Raj, Ritik, et al.
Published: (2025)
by: Raj, Ritik, et al.
Published: (2025)
Cleaning up the Mess: Re-Evaluating the Real-System Modeling Accuracy of Ramulator 2.0
by: Bostanci, F. Nisa, et al.
Published: (2025)
by: Bostanci, F. Nisa, et al.
Published: (2025)
Quantum Hardware Roofline: Evaluating the Impact of Gate Expressivity on Quantum Processor Design
by: Kalloor, Justin, et al.
Published: (2024)
by: Kalloor, Justin, et al.
Published: (2024)
ONNXim: A Fast, Cycle-level Multi-core NPU Simulator
by: Ham, Hyungkyu, et al.
Published: (2024)
by: Ham, Hyungkyu, et al.
Published: (2024)
Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators
by: Liu, Qunyou, et al.
Published: (2025)
by: Liu, Qunyou, et al.
Published: (2025)
PPU: Design and Implementation of a Pipelined Full Posit Processing Unit
by: Rossi, Federico, et al.
Published: (2023)
by: Rossi, Federico, et al.
Published: (2023)
Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs
by: Perdomo, Elias, et al.
Published: (2024)
by: Perdomo, Elias, et al.
Published: (2024)
Strassen Multisystolic Array Hardware Architectures
by: Pogue, Trevor E., et al.
Published: (2025)
by: Pogue, Trevor E., et al.
Published: (2025)
CXLMemSim: A pure software simulated CXL.mem for performance characterization
by: Yang, Yiwei, et al.
Published: (2023)
by: Yang, Yiwei, et al.
Published: (2023)
Karatsuba Matrix Multiplication and its Efficient Custom Hardware Implementations
by: Pogue, Trevor E., et al.
Published: (2025)
by: Pogue, Trevor E., et al.
Published: (2025)
ChatNeuroSim: An LLM Agent Framework for Automated Compute-in-Memory Accelerator Deployment and Optimization
by: Lee, Ming-Yen, et al.
Published: (2026)
by: Lee, Ming-Yen, et al.
Published: (2026)
Toward A Formalized Approach for Spike Sorting Algorithms and Hardware Evaluation
by: Zhang, Tim, et al.
Published: (2022)
by: Zhang, Tim, et al.
Published: (2022)
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
by: Abi-Karam, Stefan, et al.
Published: (2024)
by: Abi-Karam, Stefan, et al.
Published: (2024)
Towards Automated and Predictive Network-Level Energy Profiling in Reconfigurable IoT Systems
by: Bocus, Mohammud J., et al.
Published: (2025)
by: Bocus, Mohammud J., et al.
Published: (2025)
CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version)
by: Lindsay, Nick, et al.
Published: (2026)
by: Lindsay, Nick, et al.
Published: (2026)
Heterogeneous Memory Benchmarking Toolkit
by: Ghaemi, Golsana, et al.
Published: (2025)
by: Ghaemi, Golsana, et al.
Published: (2025)
Adaptive Cache Pollution Control for Large Language Model Inference Workloads Using Temporal CNN-Based Prediction and Priority-Aware Replacement
by: Liu, Songze, et al.
Published: (2025)
by: Liu, Songze, et al.
Published: (2025)
Recurrent CircuitSAT Sampling for Sequential Circuits
by: Ardakani, Arash, et al.
Published: (2025)
by: Ardakani, Arash, et al.
Published: (2025)
Introducing the Arm-membench Throughput Benchmark
by: Burth, Cyrill, et al.
Published: (2025)
by: Burth, Cyrill, et al.
Published: (2025)
Enhancing software-hardware co-design for HEP by low-overhead profiling of single- and multi-threaded programs on diverse architectures with Adaptyst
by: Graczyk, Maksymilian, et al.
Published: (2025)
by: Graczyk, Maksymilian, et al.
Published: (2025)
AI Load Dynamics--A Power Electronics Perspective
by: Li, Yuzhuo, et al.
Published: (2025)
by: Li, Yuzhuo, et al.
Published: (2025)
SAHM: State-Aware Heterogeneous Multicore for Single-Thread Performance
by: Wadle, Shayne, et al.
Published: (2025)
by: Wadle, Shayne, et al.
Published: (2025)
An Analytical Cost Model for Fast Evaluation of Multiple Compute-Engine CNN Accelerators
by: Qararyah, Fareed, et al.
Published: (2025)
by: Qararyah, Fareed, et al.
Published: (2025)
Characterizing and Optimizing Realistic Workloads on a Commercial Compute-in-SRAM Device
by: Zhang, Niansong, et al.
Published: (2025)
by: Zhang, Niansong, et al.
Published: (2025)
GeneTEK: Low-power, high-performance and scalable FPGA architecture for exact unit-cost edit distance
by: Espinosa, Elena, et al.
Published: (2025)
by: Espinosa, Elena, et al.
Published: (2025)
Análisis de rendimiento y eficiencia energética en el cluster Raspberry Pi Cronos
by: Semken, Martha, et al.
Published: (2025)
by: Semken, Martha, et al.
Published: (2025)
How to Increase Energy Efficiency with a Single Linux Command
by: Jelvani, Alborz, et al.
Published: (2025)
by: Jelvani, Alborz, et al.
Published: (2025)
DEER: Deep Runahead for Instruction Prefetching on Modern Mobile Workloads
by: Vahdatniya, Parmida, et al.
Published: (2025)
by: Vahdatniya, Parmida, et al.
Published: (2025)
A Review on Proprietary Accelerators for Large Language Models
by: Park, Sihyeong, et al.
Published: (2025)
by: Park, Sihyeong, et al.
Published: (2025)
Enhancing Instruction Prefetching via Cache and TLB Management
by: Jamet, Alexandre Valentin, et al.
Published: (2026)
by: Jamet, Alexandre Valentin, et al.
Published: (2026)
ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM
by: Zuepke, Alexander, et al.
Published: (2026)
by: Zuepke, Alexander, et al.
Published: (2026)
Towards CPU Performance Prediction: New Challenge Benchmark Dataset and Novel Approach
by: Liu, Xiaoman
Published: (2024)
by: Liu, Xiaoman
Published: (2024)
Similar Items
-
LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization
by: Sarkar, Rishov, et al.
Published: (2024) -
FIFOAdvisor: A DSE Framework for Automated FIFO Sizing of High-Level Synthesis Designs
by: Abi-Karam, Stefan, et al.
Published: (2025) -
Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim
by: Ali, Wajid, et al.
Published: (2025) -
SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs
by: Dang, Jingtian, et al.
Published: (2026) -
ACALSim: A Scalable Parallel Simulation Framework for High-Performance System Design Space Exploration
by: Lin, Wei-Fen, et al.
Published: (2026)