RARO: Reliability-aware Conversion with Enhanced Read Performance for QLC SSDs
Fuente:
arXiv
Guardado en:
| Autores principales: | , , , , , |
|---|---|
| Formato: | Preprint |
| Publicado: |
2025
|
| Materias: | |
| Acceso en línea: | |
| Etiquetas: |
Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
|
| _version_ | 1866912556159860736 |
|---|---|
| author | Wang, Yanyun Yu, Dingcui Lv, Yina Song, Yunpeng Zhao, Yumiao Shi, Liang |
| author_facet | Wang, Yanyun Yu, Dingcui Lv, Yina Song, Yunpeng Zhao, Yumiao Shi, Liang |
| contents | Quad-level cell (QLC) flash offers significant benefits in cost and capacity, but its limited reliability leads to frequent read retries, which severely degrade read performance. A common strategy in high-density flash storage is to program selected blocks in a low-density mode (SLC), sacrificing some capacity to achieve higher I/O performance. This hybrid storage architecture has been widely adopted in consumer-grade storage systems. However, existing hybrid storage schemes typically focus on write performance and rely solely on data temperature for migration decisions. This often results in excessive mode switching, causing substantial capacity overhead.
In this paper, we present RARO (Reliability-Aware Read performance Optimization), a hybrid flash management scheme designed to improve read performance with minimal capacity cost. The key insight behind RARO is that much of the read slowdown in QLC flash is caused by read retries. RARO triggers data migration only when hot data resides in QLC blocks experiencing a high number of read retries, significantly reducing unnecessary conversions and capacity loss. Moreover, RARO supports fine-grained multi-mode conversions (SLC-TLC-QLC) to further minimize capacity overhead. By leveraging real-time read retry statistics and flash characteristics, RARO mitigates over-conversion and optimizes I/O performance. Experiments on the FEMU platform demonstrate that RARO significantly improves read performance across diverse workloads, with negligible impact on usable capacity. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_19530 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | RARO: Reliability-aware Conversion with Enhanced Read Performance for QLC SSDs Wang, Yanyun Yu, Dingcui Lv, Yina Song, Yunpeng Zhao, Yumiao Shi, Liang Hardware Architecture Quad-level cell (QLC) flash offers significant benefits in cost and capacity, but its limited reliability leads to frequent read retries, which severely degrade read performance. A common strategy in high-density flash storage is to program selected blocks in a low-density mode (SLC), sacrificing some capacity to achieve higher I/O performance. This hybrid storage architecture has been widely adopted in consumer-grade storage systems. However, existing hybrid storage schemes typically focus on write performance and rely solely on data temperature for migration decisions. This often results in excessive mode switching, causing substantial capacity overhead. In this paper, we present RARO (Reliability-Aware Read performance Optimization), a hybrid flash management scheme designed to improve read performance with minimal capacity cost. The key insight behind RARO is that much of the read slowdown in QLC flash is caused by read retries. RARO triggers data migration only when hot data resides in QLC blocks experiencing a high number of read retries, significantly reducing unnecessary conversions and capacity loss. Moreover, RARO supports fine-grained multi-mode conversions (SLC-TLC-QLC) to further minimize capacity overhead. By leveraging real-time read retry statistics and flash characteristics, RARO mitigates over-conversion and optimizes I/O performance. Experiments on the FEMU platform demonstrate that RARO significantly improves read performance across diverse workloads, with negligible impact on usable capacity. |
| title | RARO: Reliability-aware Conversion with Enhanced Read Performance for QLC SSDs |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.19530 |