Large Language Models (LLMs) for Electronic Design Automation (EDA)
Fuente:
arXiv
Saved in:
| Main Authors: | Xu, Kangwei, Schwachhofer, Denis, Blocklove, Jason, Polian, Ilia, Domanski, Peter, Pflüger, Dirk, Garg, Siddharth, Karri, Ramesh, Sinanoglu, Ozgur, Knechtel, Johann, Zhao, Zhuorui, Schlichtmann, Ulf, Li, Bing |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026)
by: Knechtel, Johann, et al.
Published: (2026)
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
by: Blocklove, Jason, et al.
Published: (2024)
by: Blocklove, Jason, et al.
Published: (2024)
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
Evaluating LLMs for Hardware Design and Test
by: Blocklove, Jason, et al.
Published: (2024)
by: Blocklove, Jason, et al.
Published: (2024)
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)
by: Roy, Prithwish Basu, et al.
Published: (2025)
From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
by: Fu, Weimin, et al.
Published: (2026)
by: Fu, Weimin, et al.
Published: (2026)
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)
by: Mankali, Lakshmi Likhitha, et al.
Published: (2024)
Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
by: Shao, Minghao, et al.
Published: (2026)
by: Shao, Minghao, et al.
Published: (2026)
VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
by: Roy, Prithwish Basu, et al.
Published: (2026)
by: Roy, Prithwish Basu, et al.
Published: (2026)
VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
by: Sreekumar, Saideep, et al.
Published: (2026)
by: Sreekumar, Saideep, et al.
Published: (2026)
C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)
by: Wang, Zeng, et al.
Published: (2024)
Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
by: Fu, Weimin, et al.
Published: (2026)
by: Fu, Weimin, et al.
Published: (2026)
VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
by: Zhao, Zhuorui, et al.
Published: (2025)
by: Zhao, Zhuorui, et al.
Published: (2025)
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)
by: Collini, Luca, et al.
Published: (2024)
Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)
by: Mashburn, Joshua, et al.
Published: (2025)
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)
by: Wang, Zeng, et al.
Published: (2025)
Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties
by: Schwachhofer, Denis, et al.
Published: (2024)
by: Schwachhofer, Denis, et al.
Published: (2024)
GUIDE: GenAI Units In Digital Design Education
by: Xiao, Weihua, et al.
Published: (2026)
by: Xiao, Weihua, et al.
Published: (2026)
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
by: Zhao, Zhuorui, et al.
Published: (2025)
by: Zhao, Zhuorui, et al.
Published: (2025)
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
by: Nakkab, Andre, et al.
Published: (2024)
by: Nakkab, Andre, et al.
Published: (2024)
VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
by: Collini, Luca, et al.
Published: (2026)
by: Collini, Luca, et al.
Published: (2026)
Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)
by: Karn, Rupesh Raj, et al.
Published: (2025)
OptINC: Optical In-Network-Computing for Scalable Distributed Learning
by: Fei, Sijie, et al.
Published: (2026)
by: Fei, Sijie, et al.
Published: (2026)
Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
by: Chowdhury, Animesh Basak, et al.
Published: (2024)
by: Chowdhury, Animesh Basak, et al.
Published: (2024)
PrefixLLM: LLM-aided Prefix Circuit Design
by: Xiao, Weihua, et al.
Published: (2024)
by: Xiao, Weihua, et al.
Published: (2024)
ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
Need for zkSpeed: Accelerating HyperPlonk for Zero-Knowledge Proofs
by: Daftardar, Alhad, et al.
Published: (2025)
by: Daftardar, Alhad, et al.
Published: (2025)
LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs
by: Saha, Akashdeep, et al.
Published: (2025)
by: Saha, Akashdeep, et al.
Published: (2025)
Memory Is All You Need: An Overview of Compute-in-Memory Architectures for Accelerating Large Language Model Inference
by: Wolters, Christopher, et al.
Published: (2024)
by: Wolters, Christopher, et al.
Published: (2024)
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)
by: Wang, Fangzhou, et al.
Published: (2024)
Classification-Based Automatic HDL Code Generation Using LLMs
by: Sun, Wenhao, et al.
Published: (2024)
by: Sun, Wenhao, et al.
Published: (2024)
ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA
by: Shi, Zhengyuan, et al.
Published: (2025)
by: Shi, Zhengyuan, et al.
Published: (2025)
PrefixGPT: Prefix Adder Optimization by a Generative Pre-trained Transformer
by: Ding, Ruogu, et al.
Published: (2025)
by: Ding, Ruogu, et al.
Published: (2025)
Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
by: DeLorenzo, Matthew, et al.
Published: (2024)
by: DeLorenzo, Matthew, et al.
Published: (2024)
Lightweight Countermeasures Against Static Power Side-Channel Attacks
by: Bhandari, Jitendra, et al.
Published: (2024)
by: Bhandari, Jitendra, et al.
Published: (2024)
EncodingNet: A Novel Encoding-based MAC Design for Efficient Neural Network Acceleration
by: Liu, Bo, et al.
Published: (2024)
by: Liu, Bo, et al.
Published: (2024)
Similar Items
-
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026) -
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
by: Blocklove, Jason, et al.
Published: (2024) -
LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
by: Bhandari, Jitendra, et al.
Published: (2024) -
Evaluating LLMs for Hardware Design and Test
by: Blocklove, Jason, et al.
Published: (2024) -
Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)