The Future of Memory: Limits and Opportunities
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arXiv
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| Main Authors: | , , , , , , , |
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| Format: | Preprint |
| Published: |
2025
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| _version_ | 1866908554046210048 |
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| author | Dayo, Samuel Liu, Shuhan Li, Peijing Levis, Philip Mitra, Subhasish Tambe, Thierry Tennenhouse, David Wong, H. -S. Philip |
| author_facet | Dayo, Samuel Liu, Shuhan Li, Peijing Levis, Philip Mitra, Subhasish Tambe, Thierry Tennenhouse, David Wong, H. -S. Philip |
| contents | Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large numbers of CPUs. We argue two practical engineering challenges, scaling and signaling, limit such designs. We propose the opposite approach. Rather than create large, shared, homogenous memories, systems explicitly break memory up into smaller slices more tightly coupled with compute elements. Leveraging advances in 2.5D/3D integration, this compute-memory node provisions private local memory, enabling accesses of node-exclusive data through micrometer-scale distances, and dramatically reduced access cost. In-package memory elements support shared state within a processor, providing far better bandwidth and energy-efficiency than DRAM, which is used as main memory for large working sets and cold data. Hardware making memory capacities and distances explicit allows software to efficiently compose this hierarchy, managing data placement and movement. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_20425 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | The Future of Memory: Limits and Opportunities Dayo, Samuel Liu, Shuhan Li, Peijing Levis, Philip Mitra, Subhasish Tambe, Thierry Tennenhouse, David Wong, H. -S. Philip Hardware Architecture Memory latency, bandwidth, capacity, and energy increasingly limit performance. In this paper, we reconsider proposed system architectures that consist of huge (many-terabyte to petabyte scale) memories shared among large numbers of CPUs. We argue two practical engineering challenges, scaling and signaling, limit such designs. We propose the opposite approach. Rather than create large, shared, homogenous memories, systems explicitly break memory up into smaller slices more tightly coupled with compute elements. Leveraging advances in 2.5D/3D integration, this compute-memory node provisions private local memory, enabling accesses of node-exclusive data through micrometer-scale distances, and dramatically reduced access cost. In-package memory elements support shared state within a processor, providing far better bandwidth and energy-efficiency than DRAM, which is used as main memory for large working sets and cold data. Hardware making memory capacities and distances explicit allows software to efficiently compose this hierarchy, managing data placement and movement. |
| title | The Future of Memory: Limits and Opportunities |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.20425 |