Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS

Fuente: arXiv
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Autores principales: de Oliveira, Antonio Victor Machado, Sarkar, Debjit, Hajimiri, Ali
Formato: Preprint
Publicado: 2025
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_version_ 1866909757363716096
author de Oliveira, Antonio Victor Machado
Sarkar, Debjit
Hajimiri, Ali
author_facet de Oliveira, Antonio Victor Machado
Sarkar, Debjit
Hajimiri, Ali
contents Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are reconstructed by reading out voltages from a 16-element electrode array and processing the data off-chip, and sources of variation in reconstruction are discussed. The EIT system presented in this work serves as a proof-of-concept towards using CMOS as a platform for co-integrated microfluidics and electronics.
format Preprint
id arxiv_https___arxiv_org_abs_2508_20431
institution arXiv
publishDate 2025
record_format arxiv
spellingShingle Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS
de Oliveira, Antonio Victor Machado
Sarkar, Debjit
Hajimiri, Ali
Instrumentation and Detectors
Signal Processing
Electrical impedance tomography with fully integrated microfluidics and electronics is presented for the first time in a CMOS chip. Chambers and electrodes are fabricated in the interconnect layers of a 65 nm CMOS chip through post-processing, enabling picoliter-volumes to be processed and imaged. Tomography maps are reconstructed by reading out voltages from a 16-element electrode array and processing the data off-chip, and sources of variation in reconstruction are discussed. The EIT system presented in this work serves as a proof-of-concept towards using CMOS as a platform for co-integrated microfluidics and electronics.
title Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS
topic Instrumentation and Detectors
Signal Processing
url https://arxiv.org/abs/2508.20431