SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators

Fuente: arXiv

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Bibliographic Details
Main Authors:	Umuroglu, Yaman, Berganski, Christoph, Jentzsch, Felix, Danilowicz, Michal, Kryjak, Tomasz, Bezaitis, Charalampos, Sjalander, Magnus, Colbert, Ian, Preusser, Thomas, Petri-Koenig, Jakoba, Blott, Michaela
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2508.21493