SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators
Fuente:
arXiv
Saved in:
| Main Authors: | , , , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866914013637509120 |
|---|---|
| author | Umuroglu, Yaman Berganski, Christoph Jentzsch, Felix Danilowicz, Michal Kryjak, Tomasz Bezaitis, Charalampos Sjalander, Magnus Colbert, Ian Preusser, Thomas Petri-Koenig, Jakoba Blott, Michaela |
| author_facet | Umuroglu, Yaman Berganski, Christoph Jentzsch, Felix Danilowicz, Michal Kryjak, Tomasz Bezaitis, Charalampos Sjalander, Magnus Colbert, Ian Preusser, Thomas Petri-Koenig, Jakoba Blott, Michaela |
| contents | While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17% for LUTs, 66% for DSPs, and 22% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2508_21493 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators Umuroglu, Yaman Berganski, Christoph Jentzsch, Felix Danilowicz, Michal Kryjak, Tomasz Bezaitis, Charalampos Sjalander, Magnus Colbert, Ian Preusser, Thomas Petri-Koenig, Jakoba Blott, Michaela Hardware Architecture While neural network quantization effectively reduces the cost of matrix multiplications, aggressive quantization can expose non-matrix-multiply operations as significant performance and resource bottlenecks on embedded systems. Addressing such bottlenecks requires a comprehensive approach to tailoring the precision across operations in the inference computation. To this end, we introduce scaled-integer range analysis (SIRA), a static analysis technique employing interval arithmetic to determine the range, scale, and bias for tensors in quantized neural networks. We show how this information can be exploited to reduce the resource footprint of FPGA dataflow neural network accelerators via tailored bitwidth adaptation for accumulators and downstream operations, aggregation of scales and biases, and conversion of consecutive elementwise operations to thresholding operations. We integrate SIRA-driven optimizations into the open-source FINN framework, then evaluate their effectiveness across a range of quantized neural network workloads and compare implementation alternatives for non-matrix-multiply operations. We demonstrate an average reduction of 17% for LUTs, 66% for DSPs, and 22% for accumulator bitwidths with SIRA optimizations, providing detailed benchmark analysis and analytical models to guide the implementation style for non-matrix layers. Finally, we open-source SIRA to facilitate community exploration of its benefits across various applications and hardware platforms. |
| title | SIRA: Scaled-Integer Range Analysis for Optimizing FPGA Dataflow Neural Network Accelerators |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2508.21493 |