Saved in:
| Main Authors: | , , , |
|---|---|
| Format: | Preprint |
| Published: |
2025
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2509.00071 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866911130377519104 |
|---|---|
| author | Liu, Shang Wang, Jing Fang, Wenji Xie, Zhiyao |
| author_facet | Liu, Shang Wang, Jing Fang, Wenji Xie, Zhiyao |
| contents | In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, we make the first attempt, SynCircuit, to generate new synthetic circuits with valid functionalities in the HDL format. SynCircuit automatically generates synthetic data using a framework with three innovative steps: 1) We propose a customized diffusion-based generative model to resolve the Directed Cyclic Graph (DCG) generation task, which has not been well explored in the AI community. 2) To ensure our circuit is valid, we enforce the circuit constraints by refining the initial graph generation outputs. 3) The Monte Carlo tree search (MCTS) method further optimizes the logic redundancy in the generated graph. Experimental results demonstrate that our proposed SynCircuit can generate more realistic synthetic circuits and enhance ML model performance in downstream circuit design tasks. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_00071 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits Liu, Shang Wang, Jing Fang, Wenji Xie, Zhiyao Machine Learning Artificial Intelligence In recent years, AI-assisted IC design methods have demonstrated great potential, but the availability of circuit design data is extremely limited, especially in the public domain. The lack of circuit data has become the primary bottleneck in developing AI-assisted IC design methods. In this work, we make the first attempt, SynCircuit, to generate new synthetic circuits with valid functionalities in the HDL format. SynCircuit automatically generates synthetic data using a framework with three innovative steps: 1) We propose a customized diffusion-based generative model to resolve the Directed Cyclic Graph (DCG) generation task, which has not been well explored in the AI community. 2) To ensure our circuit is valid, we enforce the circuit constraints by refining the initial graph generation outputs. 3) The Monte Carlo tree search (MCTS) method further optimizes the logic redundancy in the generated graph. Experimental results demonstrate that our proposed SynCircuit can generate more realistic synthetic circuits and enhance ML model performance in downstream circuit design tasks. |
| title | SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits |
| topic | Machine Learning Artificial Intelligence |
| url | https://arxiv.org/abs/2509.00071 |