Cover Image

Bit Transition Reduction by Data Transmission Ordering in NoC-based DNN Accelerator

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Chen, Yizhi, Li, Jingwei, Zhu, Wenyao, Lu, Zhonghai
Format:	Preprint
Published:	2025
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

Travel Time Based Task Mapping for NoC-Based DNN Accelerator
by: Chen, Yizhi, et al.
Published: (2024)

CompAir: Synergizing Complementary PIMs and In-Transit NoC Computation for Efficient LLM Acceleration
by: Li, Hongyi, et al.
Published: (2025)

Demystifying FPGA Hard NoC Performance
by: Liu, Sihao, et al.
Published: (2025)

SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
by: Jung, Victor J. B., et al.
Published: (2023)

SoMa: Identifying, Exploring, and Understanding the DRAM Communication Scheduling Space for DNN Accelerators
by: Cai, Jingwei, et al.
Published: (2025)

Learning Cache Coherence Traffic for NoC Routing Design
by: Xiong, Guochu, et al.
Published: (2025)

PIMCOMP: An End-to-End DNN Compiler for Processing-In-Memory Accelerators
by: Sun, Xiaotian, et al.
Published: (2024)

'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators
by: Han, Ruichi, et al.
Published: (2026)

LEAP: LLM Inference on Scalable PIM-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelism
by: Wang, Yimin, et al.
Published: (2025)

DORA: Dataflow-Instruction Orchestration Architecture for DNN Acceleration
by: Chen, Xingzhen, et al.
Published: (2026)

METRO: A Software-Hardware Co-Design of Interconnections for Spatial DNN Accelerators
by: Wang, Zhao, et al.
Published: (2021)

A Lightweight High-Throughput Collective-Capable NoC for Large-Scale ML Accelerators
by: Colagrande, Luca, et al.
Published: (2026)

FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators
by: Jia, Shuao, et al.
Published: (2025)

FILCO: Flexible Composing Architecture with Real-Time Reconfigurability for DNN Acceleration
by: Chen, Xingzhen, et al.
Published: (2026)

Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators
by: Zhao, Shixin, et al.
Published: (2025)

Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity
by: Kam, Dongyun, et al.
Published: (2024)

SimulatorCoder: DNN Accelerator Simulator Code Generation and Optimization via Large Language Models
by: Xia, Yuhuan, et al.
Published: (2026)

Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-based Accelerators
by: Das, Abhijit, et al.
Published: (2022)

Voyager: An End-to-End Framework for Design-Space Exploration and Generation of DNN Accelerators
by: Prabhu, Kartik, et al.
Published: (2025)

Instruction-Based Coordination of Heterogeneous Processing Units for Acceleration of DNN Inference
by: Petropoulos, Anastasios, et al.
Published: (2025)

SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy
by: Xuan, Wei, et al.
Published: (2025)

Energy-Aware Heterogeneous Federated Learning via Approximate DNN Accelerators
by: Pfeiffer, Kilian, et al.
Published: (2024)

A Bit Level Weight Reordering Strategy Based on Column Similarity to Explore Weight Sparsity in RRAM-based NN Accelerator
by: Yang, Weiping, et al.
Published: (2025)

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation
by: Tagata, Hiroto, et al.
Published: (2025)

All-rounder: A Flexible AI Accelerator with Diverse Data Format Support and Morphable Structure for Multi-DNN Processing
by: Noh, Seock-Hwan, et al.
Published: (2023)

Late Breaking Results: Leveraging Approximate Computing for Carbon-Aware DNN Accelerators
by: Panteleaki, Aikaterini Maria, et al.
Published: (2025)

Facial Expression Recognition System Using DNN Accelerator with Multi-threading on FPGA
by: Ando, Takuto, et al.
Published: (2025)

NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator
by: Upadhyay, Mohit, et al.
Published: (2024)

Hardware-Aware DNN Compression for Homogeneous Edge Devices
by: Zhang, Kunlong, et al.
Published: (2025)

Platinum: Path-Adaptable LUT-Based Accelerator Tailored for Low-Bit Weight Matrix Multiplication
by: Shan, Haoxuan, et al.
Published: (2025)

HeatSense: Intelligent Thermal Anomaly Detection for Securing NoC-Enabled MPSoCs
by: Hasanzadeh, Mahdi, et al.
Published: (2025)

DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization
by: Ren, Yi, et al.
Published: (2025)

always_comm: An FPGA-based Hardware Accelerator for Audio/Video Compression and Transmission
by: Parthasarathy, Rishab, et al.
Published: (2025)

BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration
by: Chen, Yuzong, et al.
Published: (2024)

MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators
by: Leon, Vasileios, et al.
Published: (2025)

Transitive Array: An Efficient GEMM Accelerator with Result Reuse
by: Guo, Cong, et al.
Published: (2025)

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
by: Sonnino, Lorenzo, et al.
Published: (2023)

FlooNoC: A 645 Gbps/link 0.15 pJ/B/hop Open-Source NoC with Wide Physical Links and End-to-End AXI4 Parallel Multi-Stream Support
by: Fischer, Tim, et al.
Published: (2024)

A 16 nm 1.60TOPS/W High Utilization DNN Accelerator with 3D Spatial Data Reuse and Efficient Shared Memory Access
by: Yi, Xiaoling, et al.
Published: (2026)

REDACTOR: eFPGA Redaction for DNN Accelerator Security
by: Baddour, Yazan, et al.
Published: (2025)