Low Power Approximate Multiplier Architecture for Deep Neural Networks
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arXiv
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| Hauptverfasser: | , , |
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| Format: | Preprint |
| Veröffentlicht: |
2025
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| _version_ | 1866911131900051456 |
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| author | Jaswal, Pragun Krishna, L. Hemanth Srinivasu, B. |
| author_facet | Jaswal, Pragun Krishna, L. Hemanth Srinivasu, B. |
| contents | This paper proposes an low power approximate multiplier architecture for deep neural network (DNN) applications. A 4:2 compressor, introducing only a single combination error, is designed and integrated into an 8x8 unsigned multiplier. This integration significantly reduces the usage of exact compressors while preserving low error rates. The proposed multiplier is employed within a custom convolution layer and evaluated on neural network tasks, including image recognition and denoising. Hardware evaluation demonstrates that the proposed design achieves up to 30.24% energy savings compared to the best among existing multipliers. In image denoising, the custom approximate convolution layer achieves improved Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) compared to other approximate designs. Additionally, when applied to handwritten digit recognition, the model maintains high classification accuracy. These results demonstrate that the proposed architecture offers a favorable balance between energy efficiency and computational precision, making it suitable for low-power AI hardware implementations. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2509_00764 |
| institution | arXiv |
| publishDate | 2025 |
| record_format | arxiv |
| spellingShingle | Low Power Approximate Multiplier Architecture for Deep Neural Networks Jaswal, Pragun Krishna, L. Hemanth Srinivasu, B. Hardware Architecture Artificial Intelligence This paper proposes an low power approximate multiplier architecture for deep neural network (DNN) applications. A 4:2 compressor, introducing only a single combination error, is designed and integrated into an 8x8 unsigned multiplier. This integration significantly reduces the usage of exact compressors while preserving low error rates. The proposed multiplier is employed within a custom convolution layer and evaluated on neural network tasks, including image recognition and denoising. Hardware evaluation demonstrates that the proposed design achieves up to 30.24% energy savings compared to the best among existing multipliers. In image denoising, the custom approximate convolution layer achieves improved Peak Signal-to-Noise Ratio (PSNR) and Structural Similarity Index Measure (SSIM) compared to other approximate designs. Additionally, when applied to handwritten digit recognition, the model maintains high classification accuracy. These results demonstrate that the proposed architecture offers a favorable balance between energy efficiency and computational precision, making it suitable for low-power AI hardware implementations. |
| title | Low Power Approximate Multiplier Architecture for Deep Neural Networks |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2509.00764 |