Low Power Approximate Multiplier Architecture for Deep Neural Networks

Documenti analoghi

• A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
  di: Jaswal, Pragun, et al.
  Pubblicazione: (2026)
• Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication
  di: Jaswal, Pragun, et al.
  Pubblicazione: (2025)
• TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
  di: Meng, Chang, et al.
  Pubblicazione: (2026)
• Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications
  di: Krishna, L. Hemanth, et al.
  Pubblicazione: (2025)
• Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization
  di: Lou, Binglei, et al.
  Pubblicazione: (2026)